[ET-VK][fix] Widen WAR barrier to a full memory dependency for reused tensors#20915
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… tensors `vTensorStorage::transition()` emitted the write-after-read (WAR) barrier with a read-only source access mask, which Vulkan treats as an execution-only dependency (no memory dependency). Some Adreno drivers drop this narrow `COMPUTE -> COMPUTE` dependency, letting the current write race the previous read. This surfaced as deterministic output corruption at the tile seams of the tiled im2col+GEMM conv2d path (the reused im2col scratch `TmpTensor`): the next tile's im2col overwrote the trailing rows of the scratch while the current tile's GEMM was still reading them. The Vulkan op impl was unchanged and passed previously only because other leased CI devices happened to serialize the tiles; a device/driver whose scheduling did not exposed the latent hazard. When the previous access was a genuine read-only (`prev_read && !prev_written && cur_written`), widen the barrier to a full `ALL_COMMANDS` execution + memory dependency so the driver reliably honors it. Scoped to the rare WAR transition, so the common first-write and RAW/WAW paths are untouched; widening a barrier is always correctness-safe. Fixes WAR hazards generically for all storage types, not just this conv. Differential Revision: [D111994459](https://our.internmc.facebook.com/intern/diff/D111994459/) ghstack-source-id: 402958244 Pull-Request: #20915
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Stack from ghstack (oldest at bottom):
vTensorStorage::transition()emitted the write-after-read (WAR) barrier with a read-only source access mask, which Vulkan treats as an execution-only dependency (no memory dependency). Some Adreno drivers drop this narrowCOMPUTE -> COMPUTEdependency, letting the current write race the previous read. This surfaced as deterministic output corruption at the tile seams of the tiled im2col+GEMM conv2d path (the reused im2col scratchTmpTensor): the next tile's im2col overwrote the trailing rows of the scratch while the current tile's GEMM was still reading them. The Vulkan op impl was unchanged and passed previously only because other leased CI devices happened to serialize the tiles; a device/driver whose scheduling did not exposed the latent hazard. When the previous access was a genuine read-only (prev_read && !prev_written && cur_written), widen the barrier to a fullALL_COMMANDSexecution + memory dependency so the driver reliably honors it. Scoped to the rare WAR transition, so the common first-write and RAW/WAW paths are untouched; widening a barrier is always correctness-safe. Fixes WAR hazards generically for all storage types, not just this conv.Differential Revision: D111994459