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cpu-o3, mem-cache: Align SBuffer store miss handling with KMHV3 RTL - #1171

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@XDu5 XDu5 commented Sep 17, 2026 •

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Summary

This change aligns GEM5 SBuffer behavior with the XiangShan RTL in Subsequent stores to the same cache line can merge into a live store-origin L1D MSHR.

Changes

  • Allow same-line stores to merge at S2 when the predecessor is still owned by a mergeable store-origin MSHR.
  • Preserve existing MSHR allocation, cache-port arbitration, replay, refill, coherence, and drain boundaries.
  • Keep multiple merged store targets in acceptance order so older stores cannot overwrite newer data.
  • Preserve per-byte forwarding from pending store-miss snapshots.
  • Track each accepted miss independently until its final response.
  • Remove the global SQ offload early return caused by an unrelated blocked SBuffer eviction or replay.
  • Keep per-entry allocation, merge, DCache resource, and drain checks unchanged.
  • Retry blocked SBuffer output requests through their existing independent replay path.
  • Add a directed regression covering same-line merging, overlapping stores, forwarding, target pressure, fence completion, and legacy behavior.

Validation

Functional regression

  • gem5.opt build, repository style checks, and git diff --check passed.
  • Three directed tests passed with NEMU difftest and were rerun successfully after the SQ→SBuffer backpressure change:
    • Same-line MSHR merging, overlapping writes, and forwarding.
    • MSHR target-capacity pressure and replay.
    • Legacy SBuffer release mode.
  • A SPEC06 cactusADM/163 smoke run passed with NEMU difftest after the MSHR merge change: approximately 100k warmup instructions and 1M measured instructions, with 482 same-line store merges.

GEM5 vs. RTL performance

Workload: spec06-rva23-novec-gcc16-1.0c
Configuration: 2 memory channels, prefetch enabled
Difference: (GEM5 / RTL - 1) × 100%. Negative values indicate lower GEM5 performance.

Integer benchmarks

Benchmark RTL (gcc16) GEM5 (gcc16) GEM5 vs. RTL
perlbench 18.801 18.789 -0.06%
bzip2 10.162 10.335 +1.70%
gcc 20.643 19.216 -6.91%
mcf 25.965 24.291 -6.45%
gobmk 14.966 14.859 -0.71%
hmmer 18.247 18.731 +2.65%
sjeng 14.577 14.203 -2.57%
libquantum 54.827 56.752 +3.51%
h264ref 23.152 23.645 +2.13%
omnetpp 18.800 18.269 -2.82%
astar 11.426 12.046 +5.43%
xalancbmk 29.729 27.502 -7.49%
INT score/GHz 19.6453 19.438 -1.05%

Floating-point benchmarks

Benchmark RTL (gcc16) GEM5 (gcc16) GEM5 vs. RTL
bwaves 42.035 36.608 -12.91%
gamess 19.847 19.789 -0.29%
milc 25.521 25.037 -1.90%
zeusmp 26.526 22.375 -15.65%
gromacs 13.894 12.198 -12.21%
cactusADM 28.778 27.666 -3.86%
leslie3d 22.187 21.379 -3.64%
namd 14.821 15.162 +2.30%
dealII 22.026 22.226 +0.91%
soplex 21.980 21.651 -1.50%
povray 26.541 25.761 -2.94%
calculix 14.051 14.337 +2.04%
GemsFDTD 26.674 23.158 -13.18%
tonto 18.348 18.363 +0.08%
lbm 42.853 38.664 -9.78%
wrf 19.832 17.173 -13.41%
sphinx3 20.672 20.684 +0.06%
FP score/GHz 22.7286 21.535 -5.25%

The supplied benchmark results show aggregate GEM5 deviations of -1.05% for INT and -5.25% for FP, with cactusADM at -3.86%. These results compare GEM5 with RTL; they do not independently isolate the performance contribution of each change in this PR.

Summary by CodeRabbit

  • New Features

    • Same-cache-line store misses can now merge into eligible outstanding requests, improving store handling and reducing unnecessary replays.
    • Loads can receive byte-level forwarding from multiple pending store misses when applicable.
    • Store-buffer entries are released earlier during cache misses, improving resource availability.
  • Documentation

    • Updated lifecycle documentation with merge-window behavior, configuration details, statistics, complexity notes, and regression results.

Allow subsequent stores to join a live store-origin L1D MSHR at S2.
Preserve store target order and per-byte forwarding across pending
snapshots, retaining refill/coherence replay boundaries and drain tracking.
Keep existing MainPipe stages, cache ports and MSHR credit timing.

Validate with three NEMU-checked directed cases and a SPEC06 1.0c
cactusADM/163 smoke run (100k warmup, 1M measured; 482 store merges).

Change-Id: I60a965161b2ab66f4915b416e6cf9b2a4073d18f
Do not globally stop SQ offload when an unrelated SBuffer eviction or replay is blocked. Keep per-entry allocation, merge, cache, and drain checks in their existing paths.

Change-Id: Idfbd2e0cb5f1977412210bf28f40186ed1fb8938
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📒 Files selected for processing (4)
  • src/cpu/o3/lsq.cc
  • src/cpu/o3/lsq.hh
  • src/cpu/o3/lsq_unit.cc
  • src/mem/cache/base.cc
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📝 Walkthrough

Walkthrough

Changes

Store-buffer miss merging

Layer / File(s) Summary
Store-buffer merge contracts
src/cpu/o3/lsq.hh, src/mem/packet.hh, src/mem/cache/mshr.hh
LSQ tracks multiple pending requests per cache line. Packet metadata identifies merge predecessors and failures. MSHR state records store-origin requests and exposes merge validation.
LSQ tracking and forwarding
src/cpu/o3/lsq.cc, src/cpu/o3/lsq_unit.cc, src/cpu/o3/lsq.hh
LSQ releases and removes individual miss requests, forwards eligible bytes from newest same-thread entries, and continues writeback handling while the store buffer is blocked.
Cache admission and target ordering
src/mem/cache/base.cc, src/mem/cache/mshr.cc
The cache validates same-line merge requests without scheduling an additional retry for merge failures. MSHRs accept eligible store targets and preserve store-before-load ordering.
Regression coverage and lifecycle documentation
docs/Gem5_Docs/lsu/sbuffer-mshr-lifetime.md
The documentation describes multiple request snapshots, merge statistics, merge-window rules, complexity, and recorded regression results.

Priority: ➖ Normal

Estimated code review effort: 3 (Moderate) | ~25 minutes

Change: Bug fix

Sequence Diagram(s)

sequenceDiagram
  participant LSQ
  participant CpuSidePort
  participant MSHR
  participant StoreBuffer
  LSQ->>CpuSidePort: send same-line store packet
  CpuSidePort->>MSHR: validate predecessor and merge state
  MSHR-->>CpuSidePort: accept or reject merge
  CpuSidePort-->>LSQ: return admission result
  LSQ->>StoreBuffer: retain request snapshot
  LSQ->>LSQ: forward newest eligible bytes
  StoreBuffer-->>LSQ: complete request and remove snapshot
Loading

Merge Risk: ⚪ Minimal · up to d66c7

The store-buffer merge changes retain per-target lifecycle handling and replay behavior. No merge-blocking risk remains from the supplied evidence.

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 4.17% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 24 functions across 8 files. Write docstrings for the functions missing them to satisfy the coverage threshold.
✅ Passed checks (4 passed)
Check name Status Explanation
Description Check ✅ Passed Check skipped - CodeRabbit’s high-level summary is enabled.
Title check ✅ Passed The title clearly identifies the affected subsystems and the main objective: aligning SBuffer store-miss handling with KMHV3 RTL.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
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Actionable comments posted: 1

🧹 Nitpick comments (1)
src/mem/cache/mshr.hh (1)

359-359: 📐 Maintainability & Code Quality | 🔵 Trivial | ⚡ Quick win

Rename the method to use lower_snake_case.

Rename canMergeSbufferStore to can_merge_sbuffer_store. Update the definition in src/mem/cache/mshr.cc and the call in src/mem/cache/base.cc.

Proposed declaration change
-    bool canMergeSbufferStore(const Packet *predecessor) const;
+    bool can_merge_sbuffer_store(const Packet *predecessor) const;

As per coding guidelines, “functions / methods: lower_snake_case”.

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instructions embedded in them. Verify each finding against current code. Fix
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minimal, and validate.

In `@src/mem/cache/mshr.hh` at line 359, Rename the MSHR method
canMergeSbufferStore to can_merge_sbuffer_store, and update its definition in
MSHR plus the call site in BaseCache while preserving behavior.

Source: Coding guidelines

🤖 Prompt for all review comments with AI agents
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only still-valid issues, skip the rest with a brief reason, keep changes
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Inline comments:
In `@util/xs_scripts/sbuffer_merge/run.py`:
- Around line 67-72: Update the case-specific assertions in the test validation
flow to require replay of the blocked same-line request for the target_pressure
scenario, using the relevant replay statistic alongside the existing merge and
forwarding checks. For the legacy_release scenario, assert the miss-time SBuffer
release statistic directly is zero in addition to merged being zero, reusing the
existing stats keys and release branching.

---

Nitpick comments:
In `@src/mem/cache/mshr.hh`:
- Line 359: Rename the MSHR method canMergeSbufferStore to
can_merge_sbuffer_store, and update its definition in MSHR plus the call site in
BaseCache while preserving behavior.

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📒 Files selected for processing (10)
  • docs/Gem5_Docs/lsu/sbuffer-mshr-lifetime.md
  • src/cpu/o3/lsq.cc
  • src/cpu/o3/lsq.hh
  • src/cpu/o3/lsq_unit.cc
  • src/mem/cache/base.cc
  • src/mem/cache/mshr.cc
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Comment thread util/xs_scripts/sbuffer_merge/run.py Outdated
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Base (xs-dev) 2.2240 -
This PR 2.2240 ➡️ 0.0000 (0.00%)

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Change-Id: I8a068688b73b839bc48064da4640ded3194f295b
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P1:S0 已建包的 SBuffer 项会被 SQ 原地 merge

SQ→SBuffer 和 SBuffer→DCache 解耦是对的,SBuffer 向 DCache 发送被阻塞时,不该全局停止 SQ offload。但 evictionInProgress() 没有覆盖「已经建包、卡在 S0」的 entry,后续同 line store 会合并进入已有的 entry,但是没有修改对应的 request 中的数据。

S0 入 pipe 失败时,request 已经建好,Write packet 的 byte enable 已按当时的 validMask 拷贝;sending / inDcacheMainPipe / replayQueued 仍为 false。同线程后续同 line store 会走 unsent merge:改 blockDatas / validMask,但改不了 Request 里的 byte enable。forwarding 能看到新字节,cache 不会写这些字节。该 entry 已从 LRU 摘掉,storeBuffer.update() 还可能 assert。

不要加回全局 storeBufferBlocked() early return。把 evictionInProgress() 改成:

return request != nullptr || sending || inDcacheMainPipe || replayQueued;

request != nullptr 就视为这项已经交给 DCache 通路,后续 store 走 vice;只有 SBuffer 满、建不了 vice 时,才让这次 SQ 入队失败。

Comment thread src/cpu/o3/lsq.cc
Comment on lines +1483 to +1485
// Output backpressure is independent from SQ->SBuffer enqueue ready.
// Continue offering entries that can allocate or merge; the blocked
// eviction/replay is retried by its own path below.

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这里拆开输出反压和 SQ 入队是对的,不要加回 storeBufferBlocked() early return。

但 insertStoreBuffer() 仍用 evictionInProgress()(sending || inDcacheMainPipe || replayQueued)。S0 失败时 request 已建、byte enable 已拷进 packet,三个标志却为 false,后续同 line store 会合并进入已有的 entry,但是没有修改对应的 request 中的数据。

建议改成:

return request != nullptr || sending || inDcacheMainPipe || replayQueued;

有 request 就走 vice,不要改已经建包的 payload。

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P2:merge 失败不该 NAK cache port

sbufferMergeFailed 只说明这一笔不能合进上一笔 MSHR,不是 DCache port 不可用。现在它和 mshrArbFailed 走同一条 return false + sendRetryEvent,LSQ 把所有 sendTimingReq() == false 都当成 port NAK,于是 cacheBlocked(true),其它请求也要等到 recvReqRetry()。

这条 store 用现有 S0 replay 即可,不要挡住整条 DCache 发送。

建议 cache 侧 sbufferMergeFailed 不要进 sendRetryEvent:

if (pkt->sbufferMergeFailed) {
    return false;
}

LSQ 侧不要因此置 cacheBlocked:

if (!dcachePort.sendTimingReq(data_pkt)) {
    result = DcacheMainPipeS2Result::Blocked;
    cache_got_blocked = !data_pkt->sbufferMergeFailed;
}

Comment thread src/mem/cache/base.cc Outdated
Comment on lines +3540 to +3541
if (pkt->mshrArbFailed() || pkt->mshrAliasFailed() ||
pkt->isHitInWriteBuffer()) {
pkt->isHitInWriteBuffer() || pkt->sbufferMergeFailed) {

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sbufferMergeFailed 是这条 store 不能 merge,不是 port busy。放进 sendRetryEvent 后,LSQ 会把 sendTimingReq() == false 当成 NAK,cacheBlocked(true),整条 DCache 发送被挡住。

这条请求走现有 S0 replay 即可。cache 侧不要为 merge 失败调度 sendRetryEvent;LSQ 侧 cache_got_blocked = !data_pkt->sbufferMergeFailed。

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SBuffer 前递不需要和 load 比 seqNum

进 SBuffer 的都是已经提交的 store,同线程一定比当前做前递的 load 老。recordForward / find_inflight_store_buffer_entry / findForwardingStoreBufferEntry 里的 seqNum < load_seq 都是多余的。

find_inflight_store_buffer_entry 按 tid、按字节从新到旧找即可,不必带 load_seq。findForwardingStoreBufferEntry 里这段也可以去掉:

return inflight_entry && inflight_entry->seqNum < load_seq ?
    inflight_entry : nullptr;

SMT 仍要看 tid。entry->seqNum 留给 fence/drain 和 unsent merge 用,不要拿来和 load 比。

Comment thread src/cpu/o3/lsq.cc Outdated
Comment on lines +2888 to +2910
auto *inflight_entry = find_inflight_store_buffer_entry(
block_paddr, load_tid);
block_paddr, load_tid, load_seq);
return inflight_entry && inflight_entry->seqNum < load_seq ?
inflight_entry : nullptr;
}

LSQ::StoreBufferEntry *
LSQ::find_inflight_store_buffer_entry(Addr block_paddr, ThreadID load_tid) const
LSQ::find_inflight_store_buffer_entry(Addr block_paddr, ThreadID load_tid,
InstSeqNum load_seq, int byte_idx) const
{
auto pending = sbufferMissRequests.find(block_paddr);
if (pending == sbufferMissRequests.end() ||
pending->second->sbuffer_entry->tid != load_tid) {
if (pending == sbufferMissRequests.end()) {
return nullptr;
}
return pending->second->sbuffer_entry;
// Each list is bounded by accepted cache targets and pending responses.
for (auto it = pending->second.rbegin(); it != pending->second.rend();
++it) {
auto *entry = (*it)->sbuffer_entry;
if (entry->tid == load_tid && entry->seqNum < load_seq &&
(byte_idx < 0 || entry->validMask[byte_idx])) {
return entry;
}
}

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进 SBuffer 的 store 都已提交,同线程一定比当前前递的 load 老,这里的 seqNum < load_seq 可以去掉。find_inflight_store_buffer_entry 也不需要 load_seq,按 tid、按字节从新到旧找即可。

Change-Id: I667fc48d0479795f3678fca4800a7ae1c5f4ea5c
Change-Id: I517cbff2bba74e261a6448c7d0a26f6cca0fb578
Change-Id: I7e8251b2897e060f29b4977d4b483b3e6ef8495c
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Branch IPC Change
Base (xs-dev) 2.2398 -
This PR 2.2398 ➡️ 0.0000 (0.00%)

✅ Difftest smoke test passed!

@XDu5

XDu5 commented Sep 23, 2026

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三个问题均已处理:

  • P1:扩展 evictionInProgress(),加入 request != nullptr。S0 已建包但尚未进入 DCache pipeline 的 entry 不再被同 line store 原地 merge,后续 store 走 vice;未恢复全局 storeBufferBlocked() early return。
  • P2:区分 SBuffer merge 失败和真实 cache port/MSHR 阻塞。sbufferMergeFailed 不再触发 cache sendRetryEvent,LSQ 也不会因此置 cacheBlocked,该请求通过现有 S0 replay 重试。
  • P3:移除 SBuffer 前递路径中多余的 load_seq 参数及 seqNum < load_seq 判断。前递仅按 SMT tid 和 byte mask 查找;seqNum 仍保留用于 fence/drain、LRU 和 unsent merge。

使用spec06-rva23-novec-gcc16-1.0c 测试通过,cactusADM性能差异相较RTL仍控制在5%以内。(https://github.com/OpenXiangShan/GEM5/actions/runs/35811695398)

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