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@OpenXiangShan

XiangShan

Open-source high-performance RISC-V processor

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  1. XiangShan XiangShan Public

    Open-source high-performance RISC-V processor

    Scala 7.3k 946

  2. XiangShan-doc XiangShan-doc Public

    Documentation for XiangShan

    Markdown 445 152

  3. HuanCun HuanCun Public

    Open-source high-performance non-blocking cache

    Scala 101 40

  4. difftest difftest Public

    Modern co-simulation framework for RISC-V CPUs

    C++ 184 109

  5. xs-env xs-env Public

    XiangShan Frontend Develop Environment

    Shell 73 76

  6. NEMU NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    C 350 144

Repositories

Showing 10 of 107 repositories
  • difftest Public

    Modern co-simulation framework for RISC-V CPUs

    OpenXiangShan/difftest's past year of commit activity
    C++ 184 MulanPSL-2.0 109 8 15 Updated Sep 21, 2026
  • OpenXiangShan/XiangShan-Dashboard's past year of commit activity
    Vue 2 0 0 4 Updated Sep 21, 2026
  • NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    OpenXiangShan/NEMU's past year of commit activity
    C 350 144 40 43 Updated Sep 21, 2026
  • XiangShan Public

    Open-source high-performance RISC-V processor

    OpenXiangShan/XiangShan's past year of commit activity
    Scala 7,271 MulanPSL-2.0 946 113 170 Updated Sep 21, 2026
  • workload-builder Public

    CI for the workloads of Xiangshan NEMU.

    OpenXiangShan/workload-builder's past year of commit activity
    Python 10 4 0 3 Updated Sep 21, 2026
  • env-scripts Public

    Scripts for XiangShan

    OpenXiangShan/env-scripts's past year of commit activity
    Tcl 18 23 0 6 Updated Sep 21, 2026
  • xs-env Public

    XiangShan Frontend Develop Environment

    OpenXiangShan/xs-env's past year of commit activity
    Shell 73 76 0 2 Updated Sep 21, 2026
  • GEM5 Public
    OpenXiangShan/GEM5's past year of commit activity
    C++ 160 BSD-3-Clause 89 25 101 Updated Sep 21, 2026
  • AME_gem5 Public
    OpenXiangShan/AME_gem5's past year of commit activity
    C++ 5 BSD-3-Clause 1 0 0 Updated Sep 21, 2026
  • XSCache Public

    Open-source L2 (RN) & LLC (HN) cache for XiangShan open-source RISC-V core. Supports CHI Issue B/C/E.b protocols.

    OpenXiangShan/XSCache's past year of commit activity
    Scala 0 7 0 6 Updated Sep 21, 2026