Open-source high-performance RISC-V processor
Scala 7.3k 946
Documentation for XiangShan
Markdown 445 152
Open-source high-performance non-blocking cache
Scala 101 40
Modern co-simulation framework for RISC-V CPUs
C++ 184 109
XiangShan Frontend Develop Environment
Shell 73 76
Super fast RISC-V ISA emulator for XiangShan processor
C 350 144
CI for the workloads of Xiangshan NEMU.
Scripts for XiangShan
Open-source L2 (RN) & LLC (HN) cache for XiangShan open-source RISC-V core. Supports CHI Issue B/C/E.b protocols.