mem: Preserve shared DTLB defaults while enabling RTL alignment

[Ergou-ren]

Keep load and store translations on the original shared data TLB by default, while providing an explicit KMHv3 switch for independent store-side L1 ownership. The mismatch document explains both modes, their performance tradeoffs, and the remaining RTL approximation.

Summary by CodeRabbit

• New Features

  • Added an optional split store-side TLB mode for RISC-V systems, enabled with --enable-store-tlb.
  • Store translations can now use a dedicated TLB while sharing downstream page-table traffic.

• Bug Fixes

  • Improved page-table walker retry handling to prevent conflicting timing requests.

• Documentation

  • Added documentation comparing XiangShan RTL and gem5 DTLB implementations.

[coderabbitai]

📝 Walkthrough

Walkthrough

Adds an optional split store-side TLB to the RISC-V MMU, routes write translations to stb when enabled, shares downstream walker traffic, updates retry handling, configures the new option, and documents DTLB behavior across RTL and gem5 modes.

Changes

Store TLB Support

Layer / File(s)	Summary
Store-TLB configuration configs/common/xiangshan.py, configs/example/kmhv3.py, configs/example/idealkmhv3.py	Adds --enable-store-tlb and conditionally applies store-TLB parameters in KHMv3 configurations.
MMU store-translation routing src/arch/generic/mmu.hh, src/arch/riscv/RiscvMMU.py, src/arch/riscv/mmu.hh, src/arch/riscv/tlb.cc	Adds stb, selects dtb or stb by translation mode, shares data walker connections through an XBar, and updates lifecycle and functional-walker handling.
Shared walker retry handling src/arch/riscv/pagetable_walker.hh, src/arch/riscv/pagetable_walker.cc	Tracks blocked timing ports and limits retries and sends until the peer permits another request.
DTLB implementation comparison docs/design-docs/README.md, docs/design-docs/mismatch/dtlb-rtl-mismatch.md	Adds a linked comparison of XiangShan RTL and gem5 DTLB organization and behavior.

Estimated code review effort: 4 (Complex) | ~45 minutes

Sequence Diagram(s)

sequenceDiagram
  participant CPU
  participant RiscvMMU
  participant DTB
  participant STB
  participant WalkerXBar
  CPU->>RiscvMMU: issue data translation
  RiscvMMU->>DTB: route read translation
  RiscvMMU->>STB: route write translation when enabled
  DTB->>WalkerXBar: submit page-table walk
  STB->>WalkerXBar: submit page-table walk
  WalkerXBar-->>RiscvMMU: return walker response
  RiscvMMU-->>CPU: return translation

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Suggested reviewers: jueshiwenli, happy-lx

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 10.00% which is insufficient. The required threshold is 80.00%.	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (4 passed)

Check name	Status	Explanation
Description Check	✅ Passed	Check skipped - CodeRabbit’s high-level summary is enabled.
Title check	✅ Passed	The title clearly captures the main change: keeping shared DTLB behavior by default while adding RTL-alignment support.
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check	✅ Passed	Check skipped because no linked issues were found for this pull request.

✨ Finishing Touches 💡 1

📝 Generate docstrings 💡

• Create stacked PR
• Commit on current branch

🧪 Generate unit tests (beta)

• Create PR with unit tests
• Commit unit tests in branch fix-dtlb

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[coderabbitai]

Actionable comments posted: 1

🤖 Prompt for all review comments with AI agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Inline comments:
In `@docs/design-docs/mismatch/dtlb-rtl-mismatch.md`:
- Around line 206-211: Update the split-mode comparison in the sections around
the `sttlb` lookup description and its corresponding summary so both modes are
described as performing one L1 lookup per store. Explain only that split mode
cannot reuse the load-side `dtb` entry and may consequently incur an additional
store-side miss/replay; remove the claim that it performs an extra store-side
lookup.

🪄 Autofix (Beta)

Fix all unresolved CodeRabbit comments on this PR:

• Push a commit to this branch (recommended)
• Create a new PR with the fixes

---

ℹ️ Review info

⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro Plus

Run ID: 9cd3879a-5404-4897-a2c4-324e2a04cf99

📥 Commits

Reviewing files that changed from the base of the PR and between 2982f62 and a019976.

📒 Files selected for processing (11)

• configs/common/xiangshan.py
• configs/example/idealkmhv3.py
• configs/example/kmhv3.py
• docs/design-docs/README.md
• docs/design-docs/mismatch/dtlb-rtl-mismatch.md
• src/arch/generic/mmu.hh
• src/arch/riscv/RiscvMMU.py
• src/arch/riscv/mmu.hh
• src/arch/riscv/pagetable_walker.cc
• src/arch/riscv/pagetable_walker.hh
• src/arch/riscv/tlb.cc

[github-actions]

🚀 Coremark Smoke Test Results

Branch	IPC	Change
Base (xs-dev)	2.2541	-
This PR	2.2541	➡️ 0.0000 (0.00%)

✅ Difftest smoke test passed!