End-to-end RTL to GDSII ASIC physical design implementation at 28nm using Synopsys DC and ICC2 with full timing closure and DRC clean signoff.
An interactive git diff for VLSI timing signoff; visually compares two STA reports before and after a design change, instantly showing which paths sped up, slowed down, or newly violated timing.
Fixed-point MAC accelerator designed to study ASIC timing closure, pipelining, and accumulation feedback in Sky130.
ASIC Physical Design of ChipTop using Cadence Innovus | Complete RTL-to-GDSII Flow | Floorplanning | Macro Placement | CTS | Routing | Timing Closure | TCL Automation
UART Safety Controller ASIC implementation project demonstrating RTL synthesis, SKY130 technology mapping, multi-corner static timing analysis (TT/SS/FF), timing closure, CDC/RDC review, and implementation readiness for ASIC physical design.
Pipelined INT8 MAC PE — Full ASIC flow on SKY130 PDK using Yosys, OpenSTA, OpenLane 2
Post-route hold-fix ECO: insert series delay cells on hold-violating capture pins to close hold timing.
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