Pas shikra - #69
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Move the PAS_ID_* definitions out of the per-platform target_config.h files into the PTA's pas_data.h so they live in one place. These IDs are really part of the PTA contract with the client rather than a platform definition; centralizing them in the PTA is a first step towards that abstraction. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Acked-by: Jerome Forissier <jerome.forissier@arm.com>
Enable CFG_DYN_CLUSTER_SHIFT in AMD Versal Gen 2, so a single binary can detect the cluster shift (cores per cluster) from the DTB at runtime instead of relying solely on the compile-time CFG_CORE_CLUSTER_SHIFT, since AMD Versal Gen 2 flavors can have a different number of cores per cluster. Also add boot_secondary_init_intc(), which was previously left to the generic no-op weak default, to call gic_init_per_cpu() on each secondary core. This ensures each core's GIC CPU interface (SGI/PPI configuration) is explicitly initialized rather than left unconfigured. Signed-off-by: Amey Avinash Raghatate <ameyavinash.raghatate@amd.com> Signed-off-by: Akshay Belsare <akshay.belsare@amd.com> Reviewed-by: Jens Wiklander <jens.wiklander@oss.qualcomm.com>
Across platform flavors, GIC memory maps may differ, resulting in different GIC redistributor (GICR) base addresses across variants. Using a hardcoded GICR_BASE causes probe_redist_base_addrs() to read from an incorrect physical address, preventing per-CPU redistributors from being correctly initialized. Fix this by reading the GICR and GICD base address at runtime from the GIC node's reg property in the external device tree, which is the authoritative source for hardware addresses. The compile-time GICR_BASE and GICD_BASE constants are retained as fallback values in case the device tree is unavailable or the GIC node is not found. The existing static register_phys_mem_pgdir() mappings for GICD_BASE and GICR_BASE are unchanged, as their 2MB PGDIR granularity already covers all known platform base addresses within the same mapped window. Signed-off-by: Amey Avinash Raghatate <ameyavinash.raghatate@amd.com> Signed-off-by: Akshay Belsare <akshay.belsare@amd.com> Reviewed-by: Jens Wiklander <jens.wiklander@oss.qualcomm.com>
Akhilesh Kumar Verma (slategrey-vision-pwrf168)
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Enable the PIL firmware authentication framework for the Shikra platform: - CFG_QCOM_QFPROM_FUSEPROV / CMD_DB / RPMH_CLIENT / QFPROM: enable fuse provisioning support (gated on !CFG_INSECURE) - CFG_QCOM_PAS_PTA: enables the PAS Pseudo-TA (S-EL1) which owns carveout mapping, segment hash verification, and bring-up sequencing - CFG_QCOM_PAS_AUTH: enables per-segment SHA-256/384 hash verification at AUTH_AND_RESET time - CFG_PAS_MD_SLOTS=8: allows up to 8 concurrent per-peripheral metadata slots within one shared TEE session - CFG_IN_TREE_EARLY_TAS: registers the qcom_pas user TA (UUID cff7d191-7ca0-4784-af13-48223b9a4fbe) so Linux remoteproc can open a TEE session for PIL bring-up - platform/shikra/subsys.c: subsystem infrastructure with empty table; individual subsystems to be added by respective subsystem teams Clock enablement (CFG_DRIVERS_CLK) is left disabled pending clock driver support. Change-Id: I74ab23235d43fcae900e5447741d2aef327016c7 Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com>
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| #include <stdint.h> | ||
| #include <tee_api_types.h> | ||
| #include <util.h> | ||
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Register: QFPROM_RAW_CRI_CM_PRIVATEn, n=0..71 | 0x1B40000 + (0x4*n)
This register begins the RAW regions for QFPROM.
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| #define QFPROM_RAW_TO_CORR(raw_addr) \ | ||
| ((raw_addr) + (QFPROM_CORR_BASE - QFPROM_RAW_BASE)) | ||
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Follow are matching from IPCAT as well.
| #define OEM_SECURE_BOOT_ADDR 0x01b40458 | ||
| #define SEC_KEY_DERIVATION_KEY_ADDR 0x01b40468 | ||
| #define IMAGE_ENCRYPTION_KEY_1_ADDR 0x01b40650 | ||
| #define USER_KEY_DERIVATION_KEY_ADDR 0x01b40668 |
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OEM_SPARE Reg. address calculation needs to be checked.
| @@ -6,6 +6,15 @@ | |||
| #ifndef TARGET_CONFIG_H | |||
| #define TARGET_CONFIG_H | |||
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Matching with IPCAT addresses, sizes for these regions.
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| #include <auth/pas_policy.h> | ||
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| static const struct pas_swid_entry pas_swid_map[] = { |
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Need to add the relevant PILs which need auth below.
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