Csrng enablement Shikra & Nord

core/arch/arm/plat-qcom/bruin/shikra/target.mk

@@ -1 +1,4 @@
-# Placeholder for target specific configs.
+# Enable the Qualcomm CSRNG hardware RNG driver.
+# Shikra uses the legacy PRNG block via HWKM MMIO.
+# Register offsets and base address are defined in target_config.h.
+$(call force,CFG_QCOM_CSRNG,y)

core/arch/arm/plat-qcom/bruin/shikra/target_config.h

@@ -14,4 +14,9 @@
 #define IMEM_BASE			UL(0x0c100000)
 #define IMEM_SIZE			UL(0x00020000)
 
+#define QCOM_RNG_REG_BASE			UL(0x04450000)
+#define QCOM_RNG_REG_SIZE			UL(0x00020000)
+#define QCOM_RNG_DATA_OUT			0x1000
+#define QCOM_RNG_STATUS				0x1004
+
 #endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/hoya/arch_config.h

@@ -11,7 +11,6 @@
 #define GICR_BASE			UL(0x17a60000)
 
 #define RAMBLUR_PIMEM_REG_BASE		UL(0x610000)
-#define QCOM_RNG_REG_BASE		UL(0x010D1000)
 
 #define AOP_MSG_RAM_BASE		UL(0x0C300000)
 #define AOP_MSG_RAM_SIZE		UL(0x00100000)

core/arch/arm/plat-qcom/hoya/kodiak/target_config.h

@@ -39,4 +39,8 @@
 #define IRIS_BASE			UL(0x0aa00000)
 #define IRIS_SIZE			ULL(0x00200000)
 
+#define QCOM_RNG_REG_BASE      UL(0x010D0000)
+#define QCOM_RNG_REG_SIZE      UL(0x00020000)
+#define QCOM_RNG_DATA_OUT      0x1000
+#define QCOM_RNG_STATUS        0x1004
 #endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/hoya/lemans/target_config.h

@@ -94,4 +94,9 @@
 
 #define TITAN_SS_BASE			UL(0x0ac00000)
 #define TITAN_SS_SIZE			UL(0x00200000)
+
+#define QCOM_RNG_REG_BASE      UL(0x010D0000)
+#define QCOM_RNG_REG_SIZE      UL(0x00020000)
+#define QCOM_RNG_DATA_OUT      0x1000
+#define QCOM_RNG_STATUS        0x1004
 #endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/wildcat/nord/target.mk

@@ -11,3 +11,7 @@ $(call force,CFG_TEE_CORE_NB_CORE,18)
 CFG_TZDRAM_START ?= 0xBC280000
 CFG_TEE_RAM_VA_SIZE ?= 0x00200000
 CFG_TA_RAM_VA_SIZE ?= 0x07B80000
+
+# Enable the Qualcomm CSRNG hardware RNG driver.
+# Register offsets and base address are defined in target_config.h.
+$(call force,CFG_QCOM_CSRNG,y)

core/arch/arm/plat-qcom/wildcat/nord/target_config.h

@@ -18,4 +18,9 @@
 #define DRAM2_BASE			ULL(0x8800000000)
 #define DRAM2_SIZE			ULL(0x3800000000)
 
+#define QCOM_RNG_REG_BASE			UL(0x010C0000)
+#define QCOM_RNG_REG_SIZE			UL(0x2000)
+#define QCOM_RNG_DATA_OUT			0x1000
+#define QCOM_RNG_STATUS				0x1004
+
 #endif /* TARGET_CONFIG_H */

core/drivers/qcom/rng/qcom-csrng.c

@@ -9,11 +9,8 @@
 #include <mm/core_memprot.h>
 #include <platform_config.h>
 #include <rng_support.h>
+#include <trace.h>
 
-#define QCOM_RNG_REG_SIZE			0x1000
-
-#define QCOM_RNG_DATA_OUT			0x0
-#define QCOM_RNG_STATUS				0x4
 #define QCOM_RNG_STATUS_DATA_AVAIL_BMSK	0x1
 
 #define QCOM_RNG_TIMEOUT_US			1000000
@@ -31,25 +28,28 @@ TEE_Result hw_get_random_bytes(void *buf, size_t len)
 	uint32_t val = 0;
 	uint64_t to = 0;
 
-	if (!rng.va)
+	if (!rng.va) {
+		EMSG("QCOM RNG: not initialized");
 		return TEE_ERROR_NOT_SUPPORTED;
+	}
 
-	if (!out || !len)
+	if (!out || !len) {
+		EMSG("QCOM RNG: invalid parameters");
 		return TEE_ERROR_BAD_PARAMETERS;
+	}
 
 	to = timeout_init_us(QCOM_RNG_TIMEOUT_US);
 	while (len) {
 		if (!(io_read32(rng.va + QCOM_RNG_STATUS) &
 		      QCOM_RNG_STATUS_DATA_AVAIL_BMSK)) {
-			if (timeout_elapsed(to))
+			if (timeout_elapsed(to)) {
+				EMSG("QCOM RNG: timeout waiting for data");
 				return TEE_ERROR_BUSY;
+			}
 			continue;
 		}
 
-		while ((val = io_read32(rng.va + QCOM_RNG_DATA_OUT)) == 0) {
-			if (timeout_elapsed(to))
-				return TEE_ERROR_BUSY;
-		}
+		val = io_read32(rng.va + QCOM_RNG_DATA_OUT);
 
 		for (size_t i = 0; i < sizeof(val) && len; i++) {
 			*out++ = (uint8_t)(val >> (i * 8));
@@ -64,8 +64,10 @@ static TEE_Result qcom_csrng_init(void)
 {
 	rng.va = (vaddr_t)core_mmu_add_mapping(MEM_AREA_IO_SEC, rng.pa,
 					       QCOM_RNG_REG_SIZE);
-	if (!rng.va)
+	if (!rng.va) {
+		EMSG("QCOM RNG: failed to map PA=0x%08"PRIxPA, rng.pa);
 		return TEE_ERROR_GENERIC;
+	}
 
 	return TEE_SUCCESS;
 }