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…glymur Add an IMEM on glymur which falls back to mmio-sram and define the PIL relocation info region as its child, for post mortem tools to locate the loaded remoteprocs. Link: https://lore.kernel.org/lkml/20260424-glymur-imem-v5-2-18ede63cf063@oss.qualcomm.com/#r Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Without this property the scheduler treats all cores as equal. Values derived from performance measurements at 825.6 MHz: - M-class cores (cpu0-cpu5, oryon-2-2): capacity-dmips-mhz = 1024 - L-class cores (cpu6-cpu17, oryon-2-1): capacity-dmips-mhz = 1372 Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
… devices Add label properties to TPDM and CTI nodes in the glymur device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Link: https://lore.kernel.org/all/20260624-add-label-node-for-glymur-v2-1-e8420fd7025f@oss.qualcomm.com/ Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
The QCB (Qualcomm Compute Board) is a board built on the Qualcomm Glymur SoC. Unlike the CRD, the QCB exposes the board in a form factor suitable for compute workloads, power measurements and oscilloscope-based hardware validation. Add a compatible for this board. Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
The QCB (Qualcomm Compute Board) is a board built on the Qualcomm Glymur SoC. Unlike the CRD, the QCB exposes the board in a form factor suitable for compute workloads, power measurements and oscilloscope-based hardware validation. Add initial device tree support for it. Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
The Mahua QCB (Qualcomm Compute Board) is a board built on the Qualcomm Mahua SoC, a 12-core variant of the Glymur QCB in an open form factor. Unlike the CRD, the QCB is suitable for compute workloads, power measurements and oscilloscope-based hardware validation. Add a compatible for this board. Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add initial device tree support for the Mahua QCB. The QCB (Qualcomm Compute Board) is a board built on the Qualcomm Mahua SoC, a 12-core variant of the Glymur QCB in an open form factor. Unlike the CRD, the QCB is suitable for compute workloads, power measurements and oscilloscope-based hardware validation. Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Reserve memory region for audio PD dynamic loading and remote heap requirements. Add the required VMID list for memory ownership transfers. Link: https://lore.kernel.org/all/20260701-glymur-audio-v1-1-2c3862d95a09@oss.qualcomm.com/ Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> Signed-off-by: Vinayak Katoch <vinayak.katoch@oss.qualcomm.com>
…PHY on Glymur The PCIe PHYs on Glymur require a reference voltage provided by REFGEN, which in turn is powered by two LDOs. Since there is no devicetree node for REFGEN, add the vdda-refgen0p9 and vdda-refgen1p2 supplies for each PCIe PHY node. Link: https://lore.kernel.org/all/20260623-phy_refgen-v2-0-4d15983bf91d@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
The TCSR clkref_en clocks gate the QREF block which provides reference clocks to the PCIe PHYs. Wire up the LDO supplies required by the QREF and refgen blocks on the CRD board. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Mahua has a different QREF topology from Glymur. Override the TCSR compatible to qcom,mahua-tcsr in mahua.dtsi, and wire up the required LDO supplies on the CRD board. Unlike the other PCIe controllers, PCIe5 PHY on Mahua gets its refclk from the CXO0 pad directly and requires no QREF clkref_en voting. Hence, point its ref clock at RPMH_CXO_CLK. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…R for glymur-qcb Wire up the required LDO supplies on the QCB board. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…R for mahua-qcb Wire up the required LDO supplies on the QCB board. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
… voltage for SD-card SD cards may need 1.8v VDDIO also to be supported, to accommodate this requirement reduce the min voltage to 1.8v for `vreg_l2b_e0` which supplies to VDDIO pin of SD card. NOTE - Since this SD card is the only client on this regulator, this change should not have any side effect on any other clients. moreover, SD card driver takes care to explicitly vote for the regulator voltage based on the SD card detection sequence. Also for stable operation of the SD card increase VDD voltage supplied by `vreg_l9b_e0` to 2.96v. Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260702094056.3755467-2-mchunara@oss.qualcomm.com/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Document the Glymur-specific SDHCI compatible in the sdhci-msm binding. Use "qcom,sdhci-msm-v5" as the fallback compatible for the MSM SDHCI v5 controller used on Glymur. Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260703-loutish-stimulating-hummingbird-aada5e@quoll/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Add support for SD card on Glymur SoC and enable the required pinctrl configurations. Co-developed-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com> Signed-off-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com> Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260702094056.3755467-4-mchunara@oss.qualcomm.com/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Enable SD card for Glymur CRD platform. Configure the vmmc/vqmmc regulators and gpio-based card detection for the platform. Co-developed-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com> Signed-off-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com> Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260702094056.3755467-5-mchunara@oss.qualcomm.com/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
The traceNoC node is the system-level Aggregator TNOC, so it must own a valid ATID that tags the whole aggregation path. It was marked compatible with "qcom,coresight-itnoc", an Interconnect TNOC, which is never assigned an ATID. As a result the aggregator had no trace ID and could not tag the merged trace. An Interconnect TNOC is a subsystem-level aggregator: it merges trace from the ATB sources within its subsystem (TPDMs and other ATB masters) and forwards the combined stream to the system-level Aggregator TNOC. It carries no ATID of its own, because the Aggregator TNOC downstream in the path already owns the ATID. Switch the node to "qcom,coresight-tnoc" so it is described as the Aggregator TNOC it is and is assigned a system trace ID. Rename the node to "tn" and use the "apb_pclk" clock name as required by the Aggregator TNOC binding. Link: https://lore.kernel.org/all/20260710-fix-tracenoc-probe-issue-v6-5-41eb36fef8d9@oss.qualcomm.com/ Fixes: 1f7d0c4 ("arm64: dts: qcom: glymur: add coresight nodes") Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device and the CTCU device serves as the control unit for the ETR device. Link: https://lore.kernel.org/all/20260714-add-ctcu-etr-for-glymur-v1-1-791de63c0713@oss.qualcomm.com/ Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
According to user manual / programming guide there is no separate PCIe phy 3A and 3B, but one 8-lane QMP PCIe Gen5 PHY which consists of two 4-lane blocks. This is also visible in memory map, where the 0xf00000 is marked as the main block with additional sub blocks for each 4-lane phys. Describing the sub phys without the rest is not correct from hardware description, even if it works. Link: https://lore.kernel.org/all/20260609141608.354186-2-krzysztof.kozlowski@oss.qualcomm.com/ Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Glymur's PCIe3a and PCIe3b controllers share a single Gen5x8 QMP PHY block that can be bifurcated into two independent x4 links, rather than each controller owning its own dedicated PHY. Add a pcie3_phy node describing the shared PHY block, add the missing PCIe3a controller node, and point both PCIe3a's and PCIe3b's port phys at &pcie3_phy (index 0 and 1 respectively) so each controller picks up its half of the bifurcated PHY. Update the GCC pipe clock parent array to reference the new PHY's clock outputs instead of the placeholders. Link: https://lore.kernel.org/all/20260717-glymur_linkmode_0717-v5-0-4f9e87a61463@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
CRD wires the shared Gen5x8 PCIe PHY's regulator supplies through board-specific PMIC rails. Add the vdda-phy, vdda-pll, and vdda-refgen0p9/1p2 supplies for &pcie3_phy. Link: https://lore.kernel.org/all/20260717-glymur_linkmode_0717-v5-0-4f9e87a61463@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Add PCIe3a required resources eg. power supplies, GPIOs. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Enable PCIe3b controller and PCIe3b PHY. Add required LDOs and GPIOs. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
The currently listed SoCCP and SoCCP DTB reserved memory regions don't align with the memory requested by the SoCCP Firmware. Fix this by updating the SoCCP/SoCCP DTB memory regions to reflect the memory region requirements of the SoCCP firmware, as described in the Glymur v21 memory map release. Link: https://lore.kernel.org/lkml/20260709-glymur-soccp-v6-3-16f70227547d@oss.qualcomm.com/ Fixes: 41b6e8d ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
…ng system resume On Glymur, display NoC errors are observed during system resume when MDSS register accesses occur before the MMCX/Display NoC path has scaled back to a voltage level sufficient for the required bandwidth. Keep the display clock controller's power-domain requirement at the turbo operating point as a temporary workaround to ensure the interconnect remains at a stable performance level during the resume sequence and avoid NoC errors triggered by early MDSS register access. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add Battery Current Limiting (BCL) hardware monitor node for pmh0101 PMIC. The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260722-qcom-bcl-hwmon-v2-6-febe2805e17b@oss.qualcomm.com
Add Battery Current Limiting (BCL) hardware monitor node for smb2370 PMIC. The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260722-qcom-bcl-hwmon-v2-10-febe2805e17b@oss.qualcomm.com
This reverts commit 2d19aee. Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
Add iris video codec to glymur SoC, which comes with significantly different powering up sequence than previous platforms, thus different clocks and resets. https://lore.kernel.org/all/20260726-glymur-v10-13-de451559e88b@oss.qualcomm.com Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile # arch/arm64/boot/dts/qcom/talos.dtsi
# Conflicts: # arch/arm64/boot/dts/qcom/qcs8300-ride.dts # drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
# Conflicts: # drivers/firmware/qcom/Kconfig # drivers/firmware/qcom/Makefile
# Conflicts: # Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml # Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml # Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml # drivers/dma/qcom/bam_dma.c # drivers/misc/fastrpc.c # drivers/soc/qcom/ubwc_config.c # sound/soc/qcom/qdsp6/q6prm.h # sound/soc/qcom/sc8280xp.c
# Conflicts: # Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile
…emory and SMMU mappings" This change have introduced an issue on multimedia builds where AudioRecord is broken on monaco-evk board. [ 153.325884] q6apm-lpass-dais 3000000.remoteproc:glink-edge:gpr:service@1:bedais: Failed to start APM port 19 [ 153.335982] q6apm-lpass-dais 3000000.remoteproc:glink-edge:gpr:service@1:bedais: ASoC error (-110): at soc_dai_trigger() on SEC_MI2S_TX [ 153.348489] MultiMedia2 Capture: ASoC error (-110): at dpcm_be_dai_trigger() on MultiMedia2 Capture [ 153.357875] MultiMedia2 Capture: ASoC error (-110): trigger FE cmd: 1 failed Revert the change for now, to fix the issue. This reverts commit cd0f5c6. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
…emory and SMMU mappings" This change have introduced an issue on multimedia builds where AudioRecord is broken on lemans-evk board. [ 840.168044] q6apm-lpass-dais 30000000.remoteproc:glink-edge:gpr:service@1:bedais: Failed to start APM port 21 [ 840.178229] q6apm-lpass-dais 30000000.remoteproc:glink-edge:gpr:service@1:bedais: ASoC error (-110): at soc_dai_trigger() on TERT_MI2S_TX [ 840.190901] MultiMedia2 Capture: ASoC error (-110): at dpcm_be_dai_trigger() on MultiMedia2 Capture [ 840.200277] MultiMedia2 Capture: ASoC error (-110): trigger FE cmd: 1 failed Revert the change for now, to fix the issue. This reverts commit f75b90a.
This change have introduced a regression on Shikra board, wherein Rx on UART Shell is stuck, and no input is accepted. Issue: qualcomm-linux#921 Revert the change for now, to fix the issue. This reverts commit 6a36c4b. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
… EVK" Compilation breaking with this change, so revert for now. This reverts commit 8c9d598. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
Compilation breaking with this change, so revert for now. This reverts commit 9455e01. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
…nchors to board file of_graph_is_present() only checks for the presence of a 'port' child node, not whether remote-endpoint is actually connected. Adding empty port anchor nodes to monaco.dtsi caused hci_qca to enter the M.2 pwrseq probe path on all monaco-based boards, including qcs8300-ride which has a soldered WCN6855 and no M.2 Key E connector. This broke BT initialization on qcs8300-ride. Fix this by moving the port/endpoint nodes from monaco.dtsi into the monaco-evk.dts board file where the M.2 connector is actually present, so that of_graph_is_present() only returns true for boards that have an M.2 Key E connector described. Fixes: 2479c6b ("FROMLIST: arm64: dts: qcom: monaco: Add graph port/endpoint anchors to pcieport0 and uart2") Link: https://lore.kernel.org/all/20260819-b4-monaco-evk-m2-v1-v3-4-988145ef65cd@oss.qualcomm.com/ Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
…gulator" This reverts commit 32998bb in favour of the upstream fix, which is applied in the following patch. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…CIe PHYs The QMP PCIe PHYs on QCS8300 require dedicated qref and refgen voltage supplies for stable operation. Without these supplies, the system may occasionally crash. Add vdda-qref-supply and vdda-refgen-supply in the board files (QCS8300-RIDE, Monaco-EVK and Monaco-Monza-SoM), and add refgen-supply in the SoC DTSI (monaco.dtsi) since refgen is an on-chip regulator shared across boards. The PHY driver votes for refgen3 directly as a workaround for a hardware issue where QREF actually depends on refgen3 rather than refgen2 as documented. Link: https://lore.kernel.org/all/20260810112735.1326807-4-ziyue.zhang@oss.qualcomm.com/ Fixes: 33967ea ("arm64: dts: qcom: qcs8300-ride: enable pcie0 interface") Fixes: cdb613a ("arm64: dts: qcom: qcs8300-ride: enable pcie1 interface") Fixes: 41e2424 ("arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1.") Fixes: 5238f4e ("arm64: dts: qcom: Add Monaco Monza SoM") Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…ault"" The kaanapali-MTP crash that prompted the workaround was due to frame done timeouts on DSI. That issue is now fixed and frame done timeouts are no longer seen on kaanapali DSI with virtual planes enabled. Virtual planes are also required for 4K display support on Kodiak (SC7280). Re-enable virtual planes by default. This reverts commit 7a17c61. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
…pub/scm/linux/kernel/git/torvalds/linux.git tech/bsp/clk 24b9b5e 32 tech/bsp/devfreq 4809534 7 tech/security/firmware-smc de7413c 6 tech/bsp/soc-infra ff6ff7b 22 tech/bsp/pinctrl 79149ef 1 tech/bsp/remoteproc 39a86aa 13 tech/bus/peripherals e6f6741 8 tech/bus/pci/all 99d5cf2 45 tech/bus/pci/phy 66e44c2 14 tech/bus/usb/dwc d90fb64 4 tech/bus/usb/phy c3aa7d5 35 tech/debug/hwtracing a3f730f 24 tech/pmic/misc 8d60b51 22 tech/mem/iommu cdc9e80 9 tech/mm/audio/all 88b8f29 8 tech/mm/camss dffc6e9 49 tech/mm/drm 83f65e1 76 tech/mm/fastrpc bff2f47 12 tech/mm/video bdcc5c4 127 tech/mm/gpu b9f2291 12 tech/mproc/rpmsg 55dc464 1 tech/net/ath 2ac1acc 21 tech/net/bluetooth 450dc5e 7 tech/pm/power f712532 16 tech/pm/thermal d525ff9 8 tech/security/crypto 1f60c0a 23 tech/security/ice beabac0 9 tech/storage/all cef1b3c 5 tech/all/dt/qcs6490 2e92fd1 28 tech/all/dt/qcs9100 754b808 24 tech/all/dt/qcs8300 a02cf61 31 tech/all/dt/qcs615 66b7e2f 11 tech/all/dt/agatti 2ca1b63 2 tech/all/dt/eliza 5338032 25 tech/all/dt/hamoa 106f486 49 tech/all/dt/glymur c5bf216 60 tech/all/dt/kaanapali d21ef73 26 tech/all/dt/pakala 450d786 9 tech/all/config 7b48e6e 78 tech/overlay/dt b895d0e 78 tech/all/workaround 219d869 12 tech/mproc/all 104969c 2 tech/noup/debug/all e473076 29 tech/hwe/unoq a2d85fe 4 early/hwe/shikra/drivers b19d2ec 184 early/hwe/shikra/dt dd90d88 130 early/hwe/lyra 8c9d598 6
Describe the Hamoa embedded controller as a thermal-sensor provider with one cell for selecting one of up to seven thermistors. The populated channels are discovered from the EC firmware capability response, while board thermal zones can reference a channel with <&ec N>. Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Register each thermistor reported by the EC thermal capability response with devm_thermal_of_zone_register(). Read signed 16-bit temperatures returned by the EC and convert the 0.1 degree Celsius values to the millidegree units expected by the thermal framework. Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Advertise one thermal-sensor cell on the embedded controller so board thermal zones can reference the firmware-reported thermistors by index. Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Describe the EC-reported SoC, keyboard, and cover temperature sensors as thermal zones on the Glymur CRD. Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
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