Test PR for KNP AND Pakala by sgaud-quic · Pull Request #70 · qualcomm-linux-stg/kernel

sgaud-quic · 2026-08-01T07:37:12Z

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dp_display_enable() currently re-trains the link if needed and then enables the pixel clock, programs the controller to start sending the pixel stream. Split these two parts into prepare/enable APIs, to support MST bridges_enable insert the MST payloads funcs between enable stream_clks and program register. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-8-ea04113e8233@oss.qualcomm.com/

… parts dp_display_disable() handles special case of when monitor is disconnected from the dongle while the dongle stays connected thereby needing a separate function dp_ctrl_off_link_stream() for this. However with a slight rework this can still be handled by keeping common paths same for regular and special case. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-9-ea04113e8233@oss.qualcomm.com/

…ed to it With MST, multiple sinks share a single DP controller, so a cached panel in msm_dp_ctrl_private can no longer represent the per-stream sink. Drop the cache and pass panel explicitly to all stream-related dp_ctrl APIs. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-10-ea04113e8233@oss.qualcomm.com/

Split dp_ctrl_off() into stream and link parts so that for MST cases we can control the link and pixel parts separately. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-11-ea04113e8233@oss.qualcomm.com/

Move the common disable steps out of the sink_count check to make the flow easier to follow. No functional change intended. Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-12-ea04113e8233@oss.qualcomm.com/

dp_bridge helpers take drm_bridge as an input and extract the dp_display object to be used in the dp_display module. Rather than doing it in a roundabout way, directly pass the dp_display object to these helpers so that the MST bridge can also re-use the same helpers. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-13-ea04113e8233@oss.qualcomm.com/

For MST, the link setup should only be done once when multiple sinks are enabled, while stream setup may run multiple times for each sink. Split the link-related preparation out of msm_dp_display_atomic_enable() so it can be called separately before the per-stream enable path. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-14-ea04113e8233@oss.qualcomm.com/

Pass struct msm_dp_panel to the display enable/disable helpers to make them easier to reuse for MST stream handling. Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260609-dp_mstclean-v7-15-ea04113e8233@oss.qualcomm.com/

With MST, each DP controller can handle multiple streams. There shall be one dp_panel for each stream but the dp_display object shall be shared among them. To represent this abstraction, create a stream_id for each DP panel which shall be dynamically assigned to actual stream IDs by the MST path. For SST, default this to stream 0. In the MST path, panels are dynamically assigned to actual stream IDs at stream enable time by the MST layer. Use the stream ID to control the pixel clock of that respective stream by extending the clock handles and state tracking of the DP pixel clock to an array of max supported streams. The maximum streams currently is 4. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-1-2ed6aee1867a@oss.qualcomm.com/

…port DP controllers across different SoCs vary in the number of concurrent MST streams they can support. Rather than hardcoding per-platform values, the number of available pixel clocks in DT serves as a natural indicator since each stream requires a dedicated pixel clock. Introduce max_stream to capture this at initialization time and expose it for the MST module to use during setup. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-2-2ed6aee1867a@oss.qualcomm.com/

…locks Add support for additional pixel register blocks (p1, p2, p3) to enable 4‑stream MST pixel clocks. Introduce the helper functions msm_dp_read_pn and msm_dp_write_pn for pixel register programming. All pixel clocks share the same register layout but use different base addresses. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-3-2ed6aee1867a@oss.qualcomm.com/

In the DP MST architecture, stream 1 shares the same link clock as stream 0 but uses different register offsets within the same link register space. Use the dp_panel's stream_id to select the correct register offsets for stream 1 in dp_catalog. Also add stream 1 register defines. Streams 2 and 3 are not covered here, as they use separate link clocks and require separate handling. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-4-2ed6aee1867a@oss.qualcomm.com/

Whenever virtual channel slot allocation changes, the DP source must send the action control trigger sequence to notify the sink about the same. This would be applicable during the start and stop of the pixel stream. Add the infrastructure to be able to send ACT packets for the DP controller when operating in MST mode. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-5-2ed6aee1867a@oss.qualcomm.com/

Add support to program the MST enable bit in the mainlink control register when an MST session is active or being disabled. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-6-2ed6aee1867a@oss.qualcomm.com/

DP stream is transmitted in transfer units only for SST case, there is no need to calculate and program TU parameters for MST case. Skip the TU programming for MST cases. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-7-2ed6aee1867a@oss.qualcomm.com/

DP MST streams share 64 MTP slots in a time-multiplexed manner. Add support for calculating the rate governor, slot allocation, and slot reservation in the DP controller. Each MST stream can reserve its slots by calling msm_dp_display_set_stream_info() from its bridge callbacks. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-8-2ed6aee1867a@oss.qualcomm.com/

…roller The VC Payload Fill (VCPF) sequence is inserted by the DP controller when stream symbols are absent, typically before a stream is disabled. Add support for triggering the VCPF sequence in the MSM DP controller. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-9-2ed6aee1867a@oss.qualcomm.com/

…se cases As per the hardware programming guide, MST_FIFO_CONSTANT_FILL must always be programmed when operating in MST mode. Ensure the register is configured accordingly. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-10-2ed6aee1867a@oss.qualcomm.com/

…o display_unprepare msm_dp_display_disable() currently mixes stream-level shutdown (disable VSC SDP, off pixel clk, clear power_on) with link-level teardown (PSM config when sink_count==0, off_link, PHY re-init or host PHY exit). For DP MST the same link is shared across multiple streams, so disabling one stream must not tear down the link. Move the link-level steps into msm_dp_display_unprepare() so that display_disable() handles only the per-stream sequence, mirroring the split already present on the prepare path (display_prepare_link vs display_set_mode / display_enable). SST behaviour is unchanged: atomic_post_disable() still calls display_disable() followed by display_unprepare() in the same order, and the cached dp->panel used inside unprepare is the same panel that was previously passed in. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-11-2ed6aee1867a@oss.qualcomm.com/

…ting a panel The atomic bridge callbacks (set_mode / enable / disable / post_disable) on dp_display currently hard-code dp->panel. For DP MST every stream has its own msm_dp_panel that the MST encoder owns, so the same enable/disable sequence needs to be invokable against an arbitrary panel. Introduce *_helper variants that take struct msm_dp_panel * and reduce the existing atomic_* callbacks to thin wrappers that pass dp->panel. No SST-path behaviour change. Also drop the static qualifier from msm_dp_display_prepare_link() and msm_dp_display_unprepare() and change them to take struct msm_dp * so the upcoming MST encoder code can drive link-level prepare/unprepare uniformly through the public API. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-12-2ed6aee1867a@oss.qualcomm.com/

…display For DP MST, the link clock and power domain resources stay on until both streams have been disabled OR we receive hotplug. Introduce an active_stream_cnt to track the number of active streams and necessary state handling. Replace the power_on variable with active_stream_cnt as power_on boolean works only for a single stream. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-13-2ed6aee1867a@oss.qualcomm.com/

…tive The bridge detect function is only applicable for SST. In MST mode, connector detection is handled by MST bridges. Skips detection for the SST bridge when MST is active. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-14-2ed6aee1867a@oss.qualcomm.com/

If the DP controller is capable of supporting multiple streams then initialize the DP sink in MST mode by programming the DP_MSTM_CTRL DPCD register to enable MST mode. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-15-2ed6aee1867a@oss.qualcomm.com/

… panel Add an API msm_dp_display_get_panel() to initialize and return a DP panel to be used by DP MST module. Since some of the fields of DP panel are private, dp_display module needs to initialize these parts and return the panel back. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-16-2ed6aee1867a@oss.qualcomm.com/

In MST mode, multiple streams share the same DP link. Track a link_ready state so msm_dp_display_prepare_link() runs only once per link and repeated calls are skipped. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-17-2ed6aee1867a@oss.qualcomm.com/

Simply initialize MST encoders for MST-capable DP controllers, and introduce msm_dp_get_mst_max_stream to query MST streams. Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-18-2ed6aee1867a@oss.qualcomm.com/

…ller For each MST capable DP controller, initialize a dp_mst module to manage its DP MST operations. The DP MST module for each controller is the central entity to manage its topology related operations as well as interfacing with the rest of the DP driver. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-19-2ed6aee1867a@oss.qualcomm.com/

Export dpu_encoder_atomic_mode_set, dpu_encoder_phys_enable and dpu_encoder_phys_disable so MST encoder helper funcs can reuse them. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-20-2ed6aee1867a@oss.qualcomm.com/

Use msm_dp_get_mst_intf_id() to get the interface ID for the DP MST controller as the intf_id is unique for each MST stream of each DP controller. For DSI/eDP/DP SST, the stream_id is always 0, so existing behavior remains unchanged. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-21-2ed6aee1867a@oss.qualcomm.com/

…aths Call drm_dp_mst_atomic_check() from msm_atomic_check() so MST-specific state, such as connector and topology changes, is validated as part of the atomic check. Hook the MST helpers into atomic_commit_setup() and atomic_commit_tail() to support non-blocking atomic commits for DisplayPort MST, and ensure MST commits properly wait for dependencies. For SST, non-blocking commits are already handled via commit_tail(), which waits for dependencies in the DRM core. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260629-msm-dp-mst-v5-22-2ed6aee1867a@oss.qualcomm.com/

Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>

…org/pub/scm/linux/kernel/git/torvalds/linux.git tech/bsp/clk d8a14b9 30 tech/bsp/devfreq 5a26797 7 tech/bsp/soc-infra ff6ff7b 22 tech/bsp/pinctrl 79149ef 1 tech/bsp/remoteproc cbd11fb 10 tech/bus/peripherals fedd8c6 6 tech/bus/pci/all ebd808f 4 tech/bus/pci/phy 1f1f4b6 7 tech/bus/usb/dwc 9dd47ad 3 tech/bus/usb/phy c3aa7d5 35 tech/debug/hwtracing d9accac 22 tech/pmic/misc 6fb618c 8 tech/mem/iommu 44df12a 8 tech/mm/audio/all 88b8f29 8 tech/mm/camss c394dfb 32 tech/mm/drm 1d1d827 64 tech/mm/fastrpc e014e35 11 tech/mm/video 590953d 36 tech/mm/gpu 0b8d9f4 7 tech/net/ath 638841e 16 tech/pm/power bb88701 13 tech/pm/thermal d36b3ee 7 tech/security/crypto c36112e 14 tech/security/ice beabac0 9 tech/storage/all d86d915 4 tech/all/dt/qcs6490 db0d97d 20 tech/all/dt/qcs9100 166356c 88 tech/all/dt/qcs8300 cd0f5c6 22 tech/all/dt/qcs615 9a58c35 9 tech/all/dt/agatti c828f10 1 tech/all/dt/hamoa fa16fdb 36 tech/all/dt/glymur aba48bf 39 tech/all/dt/kaanapali c637991 19 tech/all/dt/pakala 960924d 13 tech/all/config 044539b 69 tech/overlay/dt 6a1064f 77 tech/all/workaround 2a67b15 26 tech/mproc/all 104969c 2 tech/noup/debug/all cbdd4bb 26 tech/hwe/unoq a2d85fe 4 early/hwe/shikra/drivers 46a583d 161 early/hwe/shikra/dt e6da759 122

On Glymur, there is an issue while working with the FP sensor connected to USB Hs only controller. The issue is as follows: 1) During boot, the usb controller initialises fine, but an error stating that the descriptor read from FP sensor failed and hence the controller is in an unknown state with failed enumeration of FP sensor. 2) At this point, the problem may be resource voting, but if unbind and rebind is done on the controller, enumeration is fine. All resources were thorughly checked and also schematic was checked to ensure that no GPIOs (if any) are left un-initialised. But resources seem to be fine. 3) When in this state, if we try to enter system suspend, GDSC too gets off, and also on resume we see that usb controller goes dead. And further attempts to enter suspend are gated by this dead controller. 4) If we re-bind controller on boot and then let enumration be successful, and then enter suspend, we see a SMMU crash on resume. On upstream code however, enumeration is fine on every reboot. This suspend-resume behavior is gating XO SD and hence disable it on CRD. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Pratham Pratap <pratham.pratap@oss.qualcomm.com>

…ng system resume On Glymur, display NoC errors are observed during system resume when MDSS register accesses occur before the MMCX/Display NoC path has scaled back to a voltage level sufficient for the required bandwidth. Keep the display clock controller's power-domain requirement at the turbo operating point as a temporary workaround to ensure the interconnect remains at a stable performance level during the resume sequence and avoid NoC errors triggered by early MDSS register access. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>

Enabling QSEECOM on Glymur CRD as below parameter is added in cmdline After the QSEECOM driver is enabled, the LoaderTpm2ActivePcrBanks UEFI variable is visible to userspace on Glymur platforms. This makes systemd wait for /dev/tpm0 during boot, but the secure TPM device is not yet enabled on Glymur. The missing TPM device adds a 90-second boot delay. Set `systemd.tpm2_wait=false` on the command line so systemd does not wait for a TPM device that is not currently available. This is a temporary change and is expected to be reverted by the end of September 2026, once the secure TPM is fully enabled on Glymur. This reverts commit e1374ed. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>

Add support for the contiguous hint (CONT) bit in ARM LPAE page tables. When a set of consecutive PTEs map a naturally-aligned contiguous block of memory, the CONT bit can be set on all entries in the group to allow the hardware to combine them into a single TLB entry, improving TLB utilization. The contiguous hint sizes per granule are: Page Size | CONT PTE | Block | CONT Block | L1 Block | CONT L1 ----------+----------+---------+------------+----------+--------- 4K | 64K | 2M | 32M | 1G | 16G 16K | 2M | 32M | 1G | | 64K | 2M | 512M | 16G | | Contiguous hint sizes are advertised in pgsize_bitmap so that IOMMU API users can align allocations to these sizes and benefit from the TLB optimization automatically. Partial unmaps of a contiguous group are rejected, ensuring the full group is always invalidated as a unit. The IO_PGTABLE_QUIRK_ARM_NO_CONT_HINT quirk allows SMMU drivers to disable contiguous hint support at runtime for hardware with implementation-specific errata. Suggested-by: Robin Murphy <robin.murphy@arm.com> Co-developed-by: Vijayanand Jitta <vijayanand.jitta@oss.qualcomm.com> Signed-off-by: Vijayanand Jitta <vijayanand.jitta@oss.qualcomm.com> Signed-off-by: Prakash Gupta <prakash.gupta@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260722-iommu_contig_hint-v3-1-10923a683441@oss.qualcomm.com/

…nule issue Qualcomm SMMU-500 has an issue with TLBIVA/TLBIVAL where only the base-page-size entry at the base IOVA is invalidated, leaving stale TLB entries for the rest of the range. This causes use-after-free: after dma_free_coherent() unmaps a large buffer, the device can still access freed physical memory through stale TLB entries. On FastRPC workloads this manifests as ADSP crashes when the ELF loader writes to a freed PA that has been reallocated. Force the TLB invalidation step granule to the minimum page size for all Qualcomm SMMU-500 domains, ensuring each page in the range is individually invalidated. The minimum page size from pgsize_bitmap is used rather than hardcoded 4K to correctly handle 16K and 64K granule configurations. This increases the number of TLB invalidation operations for large ranges, but correctness takes precedence. Signed-off-by: Prakash Gupta <prakash.gupta@oss.qualcomm.com> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>

…omain When the remoteproc has an IOMMU (kernel running at EL2 without a separate hypervisor), memory carveouts must be explicitly mapped into the remoteproc's IOMMU domain so the DSP can access them. Without this mapping the DSP triggers an SMMU translation fault when accessing the remote heap carveout used for audio PD static process creation. Add has_iommu to fastrpc_channel_ctx, set from the "iommus" property of the remoteproc DT node. When set, map the ADSP remote heap carveout into the remoteproc's IOMMU domain using an identity mapping (IOVA == PA) via iommu_map(), and skip qcom_scm_assign_mem() which is only needed when a separate hypervisor manages inter-VM memory access control. Introduce fastrpc_remote_heap_map() and fastrpc_remote_heap_unmap() helpers to encapsulate the IOMMU domain lookup and map/unmap. Link: https://lore.kernel.org/all/20260618-audio_fix_clean_v3-v1-1-ec1ee66fe455@oss.qualcomm.com/ Signed-off-by: Anandu Krishnan E <anandu.e@oss.qualcomm.com>

…ling support The Qualcomm Crypto Engine (QCE) driver currently lacks support for runtime power management (PM) and interconnect bandwidth control. As a result, the hardware remains fully powered and clocks stay enabled even when the device is idle. Additionally, static interconnect bandwidth votes are held indefinitely, preventing the system from reclaiming unused bandwidth. Address this by enabling runtime PM and dynamic interconnect bandwidth scaling to allow the system to suspend the device when idle and scale interconnect usage based on actual demand. Improve overall system efficiency by reducing power usage and optimizing interconnect resource allocation. Signed-off-by: Udit Tiwari <udit.tiwari@oss.qualcomm.com> Tested-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260517105233.807935-1-udit.tiwari@oss.qualcomm.com

Enable CONFIG_HOTPLUG_PCI_PCIE to support native PCIe hotplug controllers on arm64 platforms. Link: https://lore.kernel.org/r/20260728-hotplug_pci-v1-1-d1f38cfb9122@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

…latforms Commit eb3b5bf ("PCI: Whitelist native hotplug ports for runtime D3"), prevented native Hotplug capable Root Ports from entering D3 citing issues on old Intel SkyLake Xeon-SP platform. But there is no reason to restrict D3 for native Hotplug capable Root Ports on DT platforms. We recently enabled D3 on non-Hotplug capable Root Ports on non-x86 platforms (specifically for DT platforms) in commit a5fb3ff ("PCI: Allow PCI bridges to go to D3Hot on all non-x86"). So do the same for native Hotplug capable Root Ports as well. To honor the above platform_pci_bridge_d3() check, allow passing this check only for DT platforms, unlike a5fb3ff, which used !CONFIG_X86 check. Link: https://lore.kernel.org/all/20260729071514.859778-1-manivannan.sadhasivam@oss.qualcomm.com/ Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>

qcomlnxci · 2026-08-01T14:00:59Z

Tests-kaanapali-mtp-multimedia

Total: 31 (✅ 26, ❌ 2, ⛔ 0, ⚠️ 3)
- Failures:
  - Probe_Failure_Check
  - BT_FW_KMD_Service

Tests-sm8750-mtp-multimedia

Total: 31 (✅ 26, ❌ 2, ⛔ 0, ⚠️ 3)
- Failures:
  - Probe_Failure_Check
  - BT_FW_KMD_Service

qcomlnxci · 2026-08-01T14:01:00Z

Test Matrix

Test Case	kaanapali-mtp-multimedia	sm8750-mtp-multimedia
BT_FW_KMD_Service	❌ Fail	❌ Fail
BT_ON_OFF	✅ Pass	✅ Pass
BT_SCAN	✅ Pass	✅ Pass
CPUFreq_Validation	✅ Pass	✅ Pass
CPU_affinity	✅ Pass	✅ Pass
DSP_AudioPD	✅ Pass	✅ Pass
Ethernet	⚠️ Skip	⚠️ Skip
Freq_Scaling	✅ Pass	✅ Pass
GIC	✅ Pass	✅ Pass
IPA	✅ Pass	✅ Pass
Interrupts	✅ Pass	✅ Pass
OpenCV	⚠️ Skip	⚠️ Skip
PCIe	✅ Pass	✅ Pass
Probe_Failure_Check	❌ Fail	❌ Fail
RMNET	✅ Pass	✅ Pass
UFS_Validation	✅ Pass	✅ Pass
USBHost	✅ Pass	✅ Pass
WiFi_Firmware_Driver	✅ Pass	✅ Pass
WiFi_OnOff	⚠️ Skip	⚠️ Skip
cdsp_remoteproc	✅ Pass	✅ Pass
hotplug	✅ Pass	✅ Pass
irq	✅ Pass	✅ Pass
kaslr	✅ Pass	✅ Pass
pinctrl	✅ Pass	✅ Pass
qcom_hwrng	✅ Pass	✅ Pass
remoteproc	✅ Pass	✅ Pass
rngtest	✅ Pass	✅ Pass
shmbridge	✅ Pass	✅ Pass
smmu	✅ Pass	✅ Pass
watchdog	✅ Pass	✅ Pass
wpss_remoteproc	✅ Pass	✅ Pass

qcomlnxci · 2026-08-01T14:01:41Z

Test jobs on 0f67251

qcomlnxci · 2026-08-02T06:04:01Z

Tests-kaanapali-mtp-multimedia

Total: 31 (✅ 26, ❌ 2, ⛔ 0, ⚠️ 3)
- Failures:
  - Probe_Failure_Check
  - BT_FW_KMD_Service

Tests-sm8750-mtp-multimedia

Total: 31 (✅ 26, ❌ 2, ⛔ 0, ⚠️ 3)
- Failures:
  - Probe_Failure_Check
  - BT_FW_KMD_Service

qcomlnxci · 2026-08-02T06:04:02Z

Test Matrix

Test Case	kaanapali-mtp-multimedia	sm8750-mtp-multimedia
BT_FW_KMD_Service	❌ Fail	❌ Fail
BT_ON_OFF	✅ Pass	✅ Pass
BT_SCAN	✅ Pass	✅ Pass
CPUFreq_Validation	✅ Pass	✅ Pass
CPU_affinity	✅ Pass	✅ Pass
DSP_AudioPD	✅ Pass	✅ Pass
Ethernet	⚠️ Skip	⚠️ Skip
Freq_Scaling	✅ Pass	✅ Pass
GIC	✅ Pass	✅ Pass
IPA	✅ Pass	✅ Pass
Interrupts	✅ Pass	✅ Pass
OpenCV	⚠️ Skip	⚠️ Skip
PCIe	✅ Pass	✅ Pass
Probe_Failure_Check	❌ Fail	❌ Fail
RMNET	✅ Pass	✅ Pass
UFS_Validation	✅ Pass	✅ Pass
USBHost	✅ Pass	✅ Pass
WiFi_Firmware_Driver	✅ Pass	✅ Pass
WiFi_OnOff	⚠️ Skip	⚠️ Skip
cdsp_remoteproc	✅ Pass	✅ Pass
hotplug	✅ Pass	✅ Pass
irq	✅ Pass	✅ Pass
kaslr	✅ Pass	✅ Pass
pinctrl	✅ Pass	✅ Pass
qcom_hwrng	✅ Pass	✅ Pass
remoteproc	✅ Pass	✅ Pass
rngtest	✅ Pass	✅ Pass
shmbridge	✅ Pass	✅ Pass
smmu	✅ Pass	✅ Pass
watchdog	✅ Pass	✅ Pass
wpss_remoteproc	✅ Pass	✅ Pass

qcomlnxci · 2026-08-02T06:04:45Z

Test jobs on 0f67251

qcomlnxci · 2026-08-02T06:54:09Z

Tests-kaanapali-mtp-multimedia

Total: 31 (✅ 26, ❌ 2, ⛔ 0, ⚠️ 3)
- Failures:
  - Probe_Failure_Check
  - BT_FW_KMD_Service

Tests-sm8750-mtp-multimedia

Total: 31 (✅ 26, ❌ 2, ⛔ 0, ⚠️ 3)
- Failures:
  - Probe_Failure_Check
  - BT_FW_KMD_Service

qcomlnxci · 2026-08-02T06:54:10Z

Test Matrix

Test Case	kaanapali-mtp-multimedia	sm8750-mtp-multimedia
BT_FW_KMD_Service	❌ Fail	❌ Fail
BT_ON_OFF	✅ Pass	✅ Pass
BT_SCAN	✅ Pass	✅ Pass
CPUFreq_Validation	✅ Pass	✅ Pass
CPU_affinity	✅ Pass	✅ Pass
DSP_AudioPD	✅ Pass	✅ Pass
Ethernet	⚠️ Skip	⚠️ Skip
Freq_Scaling	✅ Pass	✅ Pass
GIC	✅ Pass	✅ Pass
IPA	✅ Pass	✅ Pass
Interrupts	✅ Pass	✅ Pass
OpenCV	⚠️ Skip	⚠️ Skip
PCIe	✅ Pass	✅ Pass
Probe_Failure_Check	❌ Fail	❌ Fail
RMNET	✅ Pass	✅ Pass
UFS_Validation	✅ Pass	✅ Pass
USBHost	✅ Pass	✅ Pass
WiFi_Firmware_Driver	✅ Pass	✅ Pass
WiFi_OnOff	⚠️ Skip	⚠️ Skip
cdsp_remoteproc	✅ Pass	✅ Pass
hotplug	✅ Pass	✅ Pass
irq	✅ Pass	✅ Pass
kaslr	✅ Pass	✅ Pass
pinctrl	✅ Pass	✅ Pass
qcom_hwrng	✅ Pass	✅ Pass
remoteproc	✅ Pass	✅ Pass
rngtest	✅ Pass	✅ Pass
shmbridge	✅ Pass	✅ Pass
smmu	✅ Pass	✅ Pass
watchdog	✅ Pass	✅ Pass
wpss_remoteproc	✅ Pass	✅ Pass

qcomlnxci · 2026-08-02T06:54:20Z

Test jobs on 0f67251

qcomlnxci · 2026-08-02T10:56:25Z

Tests-kaanapali-mtp-multimedia

Total: 31 (✅ 26, ❌ 2, ⛔ 0, ⚠️ 3)
- Failures:
  - Probe_Failure_Check
  - BT_FW_KMD_Service

Tests-sm8750-mtp-multimedia

Total: 31 (✅ 26, ❌ 2, ⛔ 0, ⚠️ 3)
- Failures:
  - Probe_Failure_Check
  - BT_FW_KMD_Service

qcomlnxci · 2026-08-02T10:56:25Z

Test Matrix

Test Case	kaanapali-mtp-multimedia	sm8750-mtp-multimedia
BT_FW_KMD_Service	❌ Fail	❌ Fail
BT_ON_OFF	✅ Pass	✅ Pass
BT_SCAN	✅ Pass	✅ Pass
CPUFreq_Validation	✅ Pass	✅ Pass
CPU_affinity	✅ Pass	✅ Pass
DSP_AudioPD	✅ Pass	✅ Pass
Ethernet	⚠️ Skip	⚠️ Skip
Freq_Scaling	✅ Pass	✅ Pass
GIC	✅ Pass	✅ Pass
IPA	✅ Pass	✅ Pass
Interrupts	✅ Pass	✅ Pass
OpenCV	⚠️ Skip	⚠️ Skip
PCIe	✅ Pass	✅ Pass
Probe_Failure_Check	❌ Fail	❌ Fail
RMNET	✅ Pass	✅ Pass
UFS_Validation	✅ Pass	✅ Pass
USBHost	✅ Pass	✅ Pass
WiFi_Firmware_Driver	✅ Pass	✅ Pass
WiFi_OnOff	⚠️ Skip	⚠️ Skip
cdsp_remoteproc	✅ Pass	✅ Pass
hotplug	✅ Pass	✅ Pass
irq	✅ Pass	✅ Pass
kaslr	✅ Pass	✅ Pass
pinctrl	✅ Pass	✅ Pass
qcom_hwrng	✅ Pass	✅ Pass
remoteproc	✅ Pass	✅ Pass
rngtest	✅ Pass	✅ Pass
shmbridge	✅ Pass	✅ Pass
smmu	✅ Pass	✅ Pass
watchdog	✅ Pass	✅ Pass
wpss_remoteproc	✅ Pass	✅ Pass

qcomlnxci · 2026-08-02T10:56:37Z

Test jobs on 0f67251

qcomlnxci · 2026-08-02T12:09:34Z

Tests-kaanapali-mtp-multimedia

Total: 31 (✅ 26, ❌ 2, ⛔ 0, ⚠️ 3)
- Failures:
  - Probe_Failure_Check
  - BT_FW_KMD_Service

Tests-sm8750-mtp-multimedia

Total: 31 (✅ 26, ❌ 2, ⛔ 0, ⚠️ 3)
- Failures:
  - Probe_Failure_Check
  - BT_FW_KMD_Service

qcomlnxci · 2026-08-02T12:09:35Z

Test Matrix

Test Case	kaanapali-mtp-multimedia	sm8750-mtp-multimedia
BT_FW_KMD_Service	❌ Fail	❌ Fail
BT_ON_OFF	✅ Pass	✅ Pass
BT_SCAN	✅ Pass	✅ Pass
CPUFreq_Validation	✅ Pass	✅ Pass
CPU_affinity	✅ Pass	✅ Pass
DSP_AudioPD	✅ Pass	✅ Pass
Ethernet	⚠️ Skip	⚠️ Skip
Freq_Scaling	✅ Pass	✅ Pass
GIC	✅ Pass	✅ Pass
IPA	✅ Pass	✅ Pass
Interrupts	✅ Pass	✅ Pass
OpenCV	⚠️ Skip	⚠️ Skip
PCIe	✅ Pass	✅ Pass
Probe_Failure_Check	❌ Fail	❌ Fail
RMNET	✅ Pass	✅ Pass
UFS_Validation	✅ Pass	✅ Pass
USBHost	✅ Pass	✅ Pass
WiFi_Firmware_Driver	✅ Pass	✅ Pass
WiFi_OnOff	⚠️ Skip	⚠️ Skip
cdsp_remoteproc	✅ Pass	✅ Pass
hotplug	✅ Pass	✅ Pass
irq	✅ Pass	✅ Pass
kaslr	✅ Pass	✅ Pass
pinctrl	✅ Pass	✅ Pass
qcom_hwrng	✅ Pass	✅ Pass
remoteproc	✅ Pass	✅ Pass
rngtest	✅ Pass	✅ Pass
shmbridge	✅ Pass	✅ Pass
smmu	✅ Pass	✅ Pass
watchdog	✅ Pass	✅ Pass
wpss_remoteproc	✅ Pass	✅ Pass

qcomlnxci · 2026-08-02T12:10:05Z

Test jobs on 0f67251

Abhinav Kumar and others added 30 commits July 10, 2026 18:42

sgaud-quic and others added 12 commits July 29, 2026 10:08

Add qcom-next log files for 20260727

269d6d8

Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>

Test PR for KNP AND Pakala

0f67251

Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>

sgaud-quic force-pushed the qcom-next-staging branch 3 times, most recently from 4020a6e to 8d3ae59 Compare August 23, 2026 10:54

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Tests-kaanapali-mtp-multimedia

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