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Fix vector CSR register sources #487

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Fix vector CSR register sources #487

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1 change: 1 addition & 0 deletions CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.

### Fixed

- Read vector CSR values from the register LSBs
- Fix dump vtrace script for vsetvli instructions without x0 (ideal dispatcher)
- Fix Pathfinder and FFT performance
- Stall Ara and wait for ara_idle upon CSR write/read
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16 changes: 8 additions & 8 deletions hardware/src/ara_dispatcher.sv
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Expand Up @@ -3394,16 +3394,16 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
acc_resp_o.result = csr_vstart_q;
end
riscv::CSR_VXRM: begin
csr_vxrm_d = vxrm_t'(acc_req_i.rs1[16:15]);
csr_vxrm_d = vxrm_t'(acc_req_i.rs1[1:0]);
acc_resp_o.result = vlen_t'(csr_vxrm_q);
end
riscv::CSR_VXSAT: begin
csr_vxsat_d = vxsat_e'(acc_req_i.rs1[15]);
csr_vxsat_d = vxsat_e'(acc_req_i.rs1[0]);
acc_resp_o.result = vlen_t'(csr_vxsat_q);
end
riscv::CSR_VCSR: begin
csr_vxrm_d = vxrm_t'( acc_req_i.rs1[17:16] );
csr_vxsat_d = vxsat_e'( acc_req_i.rs1[15] );
csr_vxrm_d = vxrm_t'( acc_req_i.rs1[2:1] );
csr_vxsat_d = vxsat_e'( acc_req_i.rs1[0] );
acc_resp_o.result = vlen_t'( { csr_vxrm_q, csr_vxsat_q } );
end
default: illegal_insn = 1'b1;
Expand Down Expand Up @@ -3432,16 +3432,16 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
else illegal_insn = 1'b1;
end
riscv::CSR_VXRM: begin
csr_vxrm_d = csr_vxrm_q | vxrm_t'(acc_req_i.rs1[16:15]);
csr_vxrm_d = csr_vxrm_q | vxrm_t'(acc_req_i.rs1[1:0]);
acc_resp_o.result = vlen_t'(csr_vxrm_q);
end
riscv::CSR_VXSAT: begin
csr_vxsat_d = csr_vxsat_q | vxsat_e'(acc_req_i.rs1[15]);
csr_vxsat_d = csr_vxsat_q | vxsat_e'(acc_req_i.rs1[0]);
acc_resp_o.result = vlen_t'(csr_vxsat_q);
end
riscv::CSR_VCSR: begin
csr_vxrm_d = csr_vxrm_q | vxrm_t'(acc_req_i.rs1[17:16]);
csr_vxsat_d = csr_vxsat_q | vxsat_e'(acc_req_i.rs1[15]);
csr_vxrm_d = csr_vxrm_q | vxrm_t'(acc_req_i.rs1[2:1]);
csr_vxsat_d = csr_vxsat_q | vxsat_e'(acc_req_i.rs1[0]);
acc_resp_o.result = vlen_t'( { csr_vxrm_q, csr_vxsat_q } );
end
default: illegal_insn = 1'b1;
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