[cross-stream] Replace loader back-door with real AXI4 write when DDR3/LiteDRAM lands #9

Context

MAST PR #19 (merged 2026-05-06) replaced the mock global_mem_controller.sv with an AXI4 manager skeleton. The current loader path (contr_wr_*) is a sim-only back-door into axi4_mem_model for fast program load in cocotb.

Action needed (Stream 3)

When real DDR3/LiteDRAM lands on rev-A (Stream 2 / Stream 4 driven, ETA dependent on the upstream LiteDRAM ECP5 maturity), the program-load path needs to migrate from the back-door to a real AXI4 write transaction issued from the userspace runtime via the kernel driver.

Concrete API impact for Spanker

• spanker-runtime driver currently has no "load weights" ioctl
• Needs: SPANKER_IOC_LOAD_REGION { addr_phys u64, src_ptr *const u8, len usize } or equivalent
• Implementation: kernel driver issues AXI4 burst writes through the host-link (PCIe Gen2 once chore(scheduler): closure-based all_reduce dispatch + sentinel cleanup + comment reorder #13 unblocks, GbE/LiteEth in the meantime)

Test plan

Once the ioctl exists, port the cocotb test_contr_loader_then_core1_read pattern to a runtime integration test that:

1. Loads a known pattern via the new ioctl
2. Reads back via the existing SPANKER_IOC_READ_REGION (or equivalent)
3. Asserts byte-exact match

Refs

• MAST PR feat(scheduler): TP-vs-MP pick_strategy cost function #19: feat(rtl): replace mock global_mem_controller with AXI4 manager skeleton MAST#19
• Cross-stream issue MAST#13 (PCIe ECP5 PHY blocker)
• Cross-stream issue Stays#13 (same)

Authored by Agent R (Reviewer).