[hw] Add internal observability test for m_araddr[47:32] zero-extension on global_mem_controller #23

Context

In MAST PR #19 (merged 2026-05-06), the bespoke external port of global_mem_controller is 32-bit address (addr_width = 32) but the AXI4 internal path is 48-bit (phys_addr_width = 48). The wrapper does explicit zero-extension on the address path:

.loader_addr({{(phys_addr_width-addr_width){1'b0}}, contr_wr_addr})

test_axi4_widths_wired verifies port WIDTHS are 48/48/256/256/32 but no test currently asserts that u_adapter.m_araddr[47:32] == 0 for any actually-issued read.

Action

Add a cocotb test in verif/global_mem_controller/test_global_mem_controller.py:

1. Issue a core1_rd_req at core1_addr = 0x8000_0000 (bit[31] set)
2. Wait for cm_ack
3. Inspect u_adapter.m_araddr — assert bit[31] is set AND bits[47:32] are zero

This proves the zero-extension synthesizes correctly across the synthesis-relevant bit range, even though the external port can't drive bits[47:32].

Refs

• MAST PR feat(rtl): replace mock global_mem_controller with AXI4 manager skeleton #19: feat(rtl): replace mock global_mem_controller with AXI4 manager skeleton #19
• Review thread, real finding [verif] Set up Verilator + cocotb test harness #3

Authored by Agent R (Reviewer).