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mellowcandle
bitwise
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docs: describe the Verilog bit select
C/C++ CI
#57:
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62ec778
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2m 34s
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man: document interactive mode and the expression syntax
C/C++ CI
#56:
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master
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Rework README
C/C++ CI
#55:
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Rework README
C/C++ CI
#54:
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Rework README
C/C++ CI
#53:
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Rework README
C/C++ CI
#52:
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Bump to version 0.7
C/C++ CI
#51:
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shunting-yard: give &, ^ and | the C precedence order
C/C++ CI
#50:
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ci: install libreadline-devel, not readline-devel, on msys2
C/C++ CI
#49:
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build: put $(top_srcdir)/inc on the include path
C/C++ CI
#48:
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docs: add CONTRIBUTING.md and a pull request template
C/C++ CI
#47:
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Makefile.am: add inc/compat.h to bitwise_SOURCES
C/C++ CI
#46:
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30s
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30s
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Bump version to 0.6
C/C++ CI
#44:
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3213035
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19s
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Add some fixes to enable build on msys2 under Windows
C/C++ CI
#43:
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fix osx build
C/C++ CI
#42:
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53f87a7
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Fix readline path resolution for Apple Silicon
C/C++ CI
#41:
Pull request
#70
synchronize by
petrostrak
19s
petrostrak:fix_readline_path_resolution_for_Apple_Silicon
petrostrak:fix_readline_path_resolution_for_Apple_Silicon
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Fix readline path resolution for Apple Silicon
C/C++ CI
#40:
Pull request
#70
opened by
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34s
petrostrak:fix_readline_path_resolution_for_Apple_Silicon
petrostrak:fix_readline_path_resolution_for_Apple_Silicon
34s
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Add set, clear, toggle and test bit operators
C/C++ CI
#39:
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0808409
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21s
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Fix modulus by zero crash and typo in lltostr
C/C++ CI
#37:
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19s
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