sync: merge upstream DangoSys/bbdev main @ 90560b4 - #2
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…ml to fix timeout bug
…ing path handling and logging
…rkload_build_dir function
….py and generate.py with bitwrite validation
…andling and adding ELF validation
Upstream changes absorbed (7 commits, merge-base b5271ca): - SRAM macro generation/replacement APIs (DangoSys#15) - tapeout output dir support in build/sim steps - motia worker exec command timeout fix - workload cleanup path handling refactor - UVM/Verilator workflow param handling + ELF validation - .gitignore: exclude lc_output.txt Fork-side intent preserved (zero file overlap with upstream): - MODEL_LAYOUT single-sourced: regression/scripts/model_layout.py imports from workload/01_build_event.step.py (dd8bc5a) - dead MODEL_CMAKE dict removed (dd8bc5a) - toy model binds: distilbert/berttiny MODEL_LAYOUT entries
This was referenced Sep 6, 2026
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同步内容
上游 DangoSys/bbdev main @
90560b4(merge-baseb5271ca，上游独有 7 commit):冲突裁决
零文件重叠（上游 62 文件 vs fork 2 文件，交集为空），无冲突合并。
Fork 意图保留验证
api/steps/regression/scripts/model_layout.py:MODEL_LAYOUT 仍单源自api/steps/workload/01_build_event.step.py(importlib 桥接）MODEL_CMAKE死字典保持零存在（grep 全仓无匹配）