Staff Engineer – FPGA Design Implementation and Prototyping at Jio Platforms Limited (Reliance Jio), Bengaluru.
I close timing on the designs everyone else gives up on. 15 years building high-performance FPGA prototypes for AI accelerators, 5G NR, and 4G LTE systems, with deep hands-on work across AMD Versal, Zynq UltraScale+ RFSoC, and Virtex-7 platforms in AMD Vivado.
Architecting the FPGA prototype for a dataflow-centric AI inference accelerator on AMD Versal (VHK158), pushing AI-driven predictive analysis and automated place-and-route into high-utilization, congested timing closure.
Building out AI-assisted automation frameworks that turn multi-pass timing closure into a repeatable, parameterized workflow instead of a manual grind.
Platform: AMD Versal – VHK158 Evaluation Kit
Led implementation and timing closure for a tile-based FPGA prototype of a dataflow-centric AI inference accelerator, managing setup and hold constraints in a high-utilization environment. Integrated AI-driven predictive analysis with automated place-and-route for critical clock domains, and built scalable, parameterized automation frameworks that cut development cycles.
Platform: AMD Zynq UltraScale+ RFSoC – XCZU67DR
Owned the end-to-end FPGA prototyping workflow for a sub-1GHz radio access system, from requirements through implementation. Custom automation scripts and cross-functional debugging cut prototype development time by 20%.
Platform: AMD Zynq UltraScale+ RFSoC – XCZU21DR
Built a rigorous timing baselining flow for a 32TX/32RX massive MIMO base station, root-causing timing issues across every design phase. Optimization of timing-critical blocks delivered a 10% Fmax improvement.
Platform: AMD Zynq UltraScale+ RFSoC – XCZU28DR
Architected a high-performance FPGA prototyping and post-implementation flow for a 3.5 GHz SU-MIMO small cell unit, hitting timing and utilization targets with minimal turnaround.
Platform: AMD Virtex-7 – XC7V2000T
Designed the prototyping framework, I/O pin mapping, and clocking network architecture for a low-power LTE Cat-M1/NB-IoT radio unit. Integrated incremental compilation using reference placement and routing data, cutting implementation time by 20%.
Platform: AMD Virtex-7 – XC7V2000T
Defined I/O pin planning and global clocking networks for a high-speed 4G LTE Cat 4 modem, closing timing on high-speed memory interfaces through floorplanning and controlled placement. Eliminated critical timing bottlenecks for a 15% Fmax improvement, and implemented OOC workflows to validate standalone module performance.
Platform: AMD Virtex-7 – XC7V2000T
Architected independent FPGA prototypes for a RISC-V core and multi-core DSP, refactoring gated clocking structures into FPGA-native architectures and building equivalent memory models via the Vivado IP catalog.
Platforms · AMD Versal, AMD Zynq UltraScale+ RFSoC, AMD Virtex-7
EDA Tools · AMD Vivado, AMD ISE, Synplify Premier, Verilator, VCS, QuestaSim
Implementation & Timing · Static Timing Analysis (STA), MCMM Timing Closure, Clock Domain Crossing (CDC), IO Planning, XDC Constraint Definition, Congestion Mitigation, Partial Reconfiguration, OOC Implementation
Scripting & Automation · Tcl, Perl, Shell, AI-driven timing closure automation
Protocols · AMBA-AXI, AHB, APB, SPI, I2C
HDL · Verilog, SystemVerilog
OS · Linux (RHEL), Windows
Award for Service Excellence — MBit Wireless Pvt. Ltd.
B.Tech, Electronics and Communication Engineering — Pondicherry University
📧 er.aswinjohn@gmail.com · 💼 LinkedIn · 📍 Bengaluru, Karnataka