ati: Correct VBL status and interrupt handling - #208
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insert_bits expects its final argument to be the field width, but both ATI VBL callbacks passed the current VBL state. When VBL ended, that meant using zero as the width, so the update was a no-op. After the first vertical blank began, the ATI_CRTC_VBLANK status bit was never cleared, confusing guest code that polls the live VBL state.
More accurately model the VBL interrupt behavior of ATI chips. When VBL begins, set the interrupt-pending bits and derive the PCI IRQ from each pending bit and its matching enable bit. Keep the pending state and PCI IRQ asserted until the guest driver acknowledges the event, even if VBL has already ended. The interrupt may therefore be asserted for less or more time than the physical VBL interval, depending on when the guest acknowledges it. This allows the driver to acknowledge the interrupt and resume other work while VBL may still be active. Previously the PCI IRQ followed the entire VBL interval, so it could remain asserted after the pending event had been acknowledged. Track the PCI IRQ output level and notify the interrupt controller only when that level changes.
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Correct two issues with ATI vertical blank handling:
This improves Mac OS X 10.4 Tiger booting on the iMac G3. The ATI driver can complete more of its display initialization, allowing the guest to progress past the apparent "Waiting for IFC" hang and into WindowServer startup.
A separate CPU timing fix is still needed for
loginwindowto connect before WindowServer's timeout.See commit messages for details.