GitHub - bkepps/EE5900_VLSI_Project: MIPS processor design in Cadence Virtuoso · GitHub

Name		Name	Last commit message	Last commit date
1_To_8_Demux/schematic		1_To_8_Demux/schematic
1bit_FullAddSub		1bit_FullAddSub
1bit_FullAdder		1bit_FullAdder
1bit_FullAdder_Testbench		1bit_FullAdder_Testbench
1to2_demux		1to2_demux
2to1mux		2to1mux
4BitOR		4BitOR
4_1_MUX_Schematic		4_1_MUX_Schematic
4_1_MUX_TestBench		4_1_MUX_TestBench
4bitAND		4bitAND
4bitOR		4bitOR
4bit_FullAddSub		4bit_FullAddSub
4bit_FullAddSub_Testbench		4bit_FullAddSub_Testbench
4bit_Register		4bit_Register
8_1_MUX		8_1_MUX
8_1_MUX_Layout/layout		8_1_MUX_Layout/layout
AND		AND
AND3		AND3
AND4		AND4
AND4_testBench		AND4_testBench
AND_testBench		AND_testBench
Barrel_Shifter		Barrel_Shifter
Barrel_Shifter_testBench		Barrel_Shifter_testBench
ControlLogic		ControlLogic
ControlLogic_testbench		ControlLogic_testbench
DFlipFlop		DFlipFlop
DFlipFlop_Testbench		DFlipFlop_Testbench
Full_Schematic		Full_Schematic
Full_Schematic_Testbench		Full_Schematic_Testbench
NAND		NAND
NOR		NOR
NOT		NOT
OR4		OR4
OR4_copy/schematic		OR4_copy/schematic
XOR		XOR
and_gate/schematic		and_gate/schematic
mux_tes/maestro		mux_tes/maestro
mux_test		mux_test
mux_testbench/maestro		mux_testbench/maestro
no_gate		no_gate
no_gate_2/symbol		no_gate_2/symbol
not_testBench		not_testBench
.oalib		.oalib
VLSI Report.pdf		VLSI Report.pdf
cdsinfo.tag		cdsinfo.tag
data.dm		data.dm

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MIPS processor design in Cadence Virtuoso

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