Pinned Loading

1. Dual_Clock_Asynchronous_FIFO_UVM Dual_Clock_Asynchronous_FIFO_UVM Public

   UVM 1.2 Verification of Dual Clock Asynchronous FIFO

   SystemVerilog 2

2. FPGA_Prototyping_SystemVerilog-Verilog FPGA_Prototyping_SystemVerilog-Verilog Public

   Solved SystemVerilog/Verilog Examples from Pong-P-Chu book

   Verilog 2 2

3. Spike_NN_ASIC Spike_NN_ASIC Public

   ASIC Design Implementation of Spike-NN based Neuromorphic Processor (benchmarked using hardcoded dummy dataset values)

   SystemVerilog 1

4. Batcher_Odd_Even_Merge_Sort_SystemC Batcher_Odd_Even_Merge_Sort_SystemC Public

   Implementation of Batcher's Odd Even Merge Sort in SystemC

   C++