Adding new node for uarlite and cleaning up#3224
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Please properly separate by logical patches. Doing too much different things in one patch. Also follow git log style. git log --no-merges --oneline arch/arm64/boot/dts for examples
| @@ -1,3 +1,4 @@ | |||
| // SPDX-License-Identifier: GPL-2.0 | |||
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not related. Please separate patch for this one.
| clkin_8000: clock@2 { | ||
| #clock-cells = <0>; | ||
| clock-frequency = <8000000000>; | ||
| clock-frequency = /bits/ 64 <8000000000>; |
Changes: all files for vu11p-ad9084-vpx now have a new node for the uartlite. Signed-off-by: Oscar Magana Pantoja <Oscar.MaganaPantoja@analog.com>
AD4630-20 and AD4632-20 are 20-bit precision ADCs and should have had their base word length set to 20. Similar logic applies to minimum and maximum offsets which should be set according to the amount of precisssion bits. Fixes: 299dc60 ("iio: adc: ad4630: Add support for AD4630-20 and AD4632-20") Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
The available list/range for sampling frequency wasn't been fully implemented and is not needed. Drop the unused attribute. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
The support of adding nvmem cells directly to the memory node is being removed in the future and has to be explicitly specified in driver nvmem configuration. By default, nvmem only adds cells from fixed-layout node. Added fixed layout node in the i2c eeprom to support loading MAC address from eeprom. Signed-off-by: Ramona Alexandra Nechita <ramona.nechita@analog.com>
Use shared action that uses pi instead of claude code, with better logging, faster install, and with session export. The inputs have been simplified, the user now selects a model size from a dropdown, and the skill set is static at the action level (no exposed prompt-repository). Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Enable LEDS_TRIGGER_DEFAULT_ON, that allows LEDs to be initialised in the ON state. Signed-off-by: Jorge Marques <jorge.marques@analog.com>
… table Fix the register address from 0x210 to 0x216 in the ADI_REC_ES_SERDES_INIT_TBL_2 initialization sequence. The previous value was incorrect and would overwrite the wrong register during SERDES PLL initialization. Fixes: 76a7e07 ("iio: frequency: ad917x: Add AD936x API driver source") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Remove duplicate semicolons on return statements in ad917x_jesd_enable_datapath(). Fixes: 76a7e07 ("iio: frequency: ad917x: Add AD936x API driver source") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Using a larger data width made SPI transfers run 4 additional bits which caused the capture data to be shifted by 4 bits. Use the correct data width for 20-bit precision ADCs, making SPI transfers run 20 SCLK pulses per transfer which in turn will make the controller gather only the expected data bits to the sample buffer. Fixes: 299dc60 ("iio: adc: ad4630: Add support for AD4630-20 and AD4632-20") Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
To allow publishing pull request comments, write permission is required. The LLM job remains with permission pull requests read, a second job with only pull requests permission write takes the llm.outputs.pr (number) and llm.outputs.commend (markdown comment) and write the comment. If a comment already exists, it updates the existing one to not clutter the pr conversation. Signed-off-by: Jorge Marques <jorge.marques@analog.com>
ad4695_enter_advanced_sequencer_mode() was called after spi_offload_trigger_enable(). That is wrong because ad4695_enter_advanced_sequencer_mode() issues regular SPI transfers to put the ADC into advanced sequencer mode, and not all SPI offload capable controllers support regular SPI transfers while offloading is enabled. Fix this by calling ad4695_enter_advanced_sequencer_mode() before spi_offload_trigger_enable(), so the ADC is fully configured before the first CNV pulse can occur. This is consistent with the same constraint that already applies to the BUSY_GP_EN write above it. Update the error unwind labels accordingly: add err_exit_conversion_mode so that a failure of spi_offload_trigger_enable() correctly exits conversion mode before clearing BUSY_GP_EN. Fixes: f09f140 ("iio: adc: ad4695: Add support for SPI offload") Reviewed-by: Nuno Sá <nuno.sa@analog.com> Reviewed-by: David Lechner <dlechner@baylibre.com> Signed-off-by: Radu Sabau <radu.sabau@analog.com>
Given that we still have dependencies on /sys/class/gpio in some of our supported board, make sure GPIO_SYSFS it it's built. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
Kconfig.adi was changed to imply GPIO_SYSFS which means deconfigs also need updating. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
Kconfig.adi was changed to imply GPIO_SYSFS which means deconfigs also need updating. Note that adi_zynqmp_defconfig already had GPIO_SYSFS but now it's removed again as we do not need to explicitly set it. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
… prevent wrong idmap generation
The PTE_MAYBE_NG macro sets the nG page table bit according to the value
of "arm64_use_ng_mappings". This variable is currently placed in the
.bss section. create_init_idmap() is called before the .bss section
initialisation which is done in early_map_kernel(). Therefore,
data/test_prot in create_init_idmap() could be set incorrectly through
the PAGE_KERNEL -> PROT_DEFAULT -> PTE_MAYBE_NG macros.
# llvm-objdump-21 --syms vmlinux-gcc | grep arm64_use_ng_mappings
ffff800082f242a8 g O .bss 0000000000000001 arm64_use_ng_mappings
The create_init_idmap() function disassembly compiled with llvm-21:
// create_init_idmap()
ffff80008255c058: d10103ff sub sp, sp, #0x40
ffff80008255c05c: a9017bfd stp x29, x30, [sp, #0x10]
ffff80008255c060: a90257f6 stp x22, x21, [sp, #0x20]
ffff80008255c064: a9034ff4 stp x20, x19, [sp, #0x30]
ffff80008255c068: 910043fd add x29, sp, #0x10
ffff80008255c06c: 90003fc8 adrp x8, 0xffff800082d54000
ffff80008255c070: d280e06a mov x10, #0x703 // =1795
ffff80008255c074: 91400409 add x9, x0, #0x1, lsl analogdevicesinc#12 // =0x1000
ffff80008255c078: 394a4108 ldrb w8, [x8, #0x290] ------------- (1)
ffff80008255c07c: f2e00d0a movk x10, #0x68, lsl analogdevicesinc#48
ffff80008255c080: f90007e9 str x9, [sp, #0x8]
ffff80008255c084: aa0103f3 mov x19, x1
ffff80008255c088: aa0003f4 mov x20, x0
ffff80008255c08c: 14000000 b 0xffff80008255c08c <__pi_create_init_idmap+0x34>
ffff80008255c090: aa082d56 orr x22, x10, x8, lsl analogdevicesinc#11 -------- (2)
Note (1) is loading the arm64_use_ng_mappings value in w8 and (2) is set
the text or data prot with the w8 value to set PTE_NG bit. If the .bss
section isn't initialized, x8 could include a garbage value and generate
an incorrect mapping.
Annotate arm64_use_ng_mappings as __read_mostly so that it is placed in
the .data section.
Fixes: 84b04d3 ("arm64: kernel: Create initial ID map from C code")
Cc: stable@vger.kernel.org # 6.9.x
Tested-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Link: https://lore.kernel.org/r/20250502180412.3774883-1-yeoreum.yun@arm.com
[catalin.marinas@arm.com: use __read_mostly instead of __ro_after_init]
[catalin.marinas@arm.com: slight tweaking of the code comment]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 363cd2b)
The USB gadget was not working due to the USB3 PHY being declared only on the child DWC3 node (snps,dwc3). The dwc3-xilinx platform driver looks for the PHY on the parent node (xlnx,zynqmp-dwc3) and, since commit ed9c7cc ("usb: dwc3: xilinx: make sure pipe clock is deselected in usb2 only mode"), actively deselects the PIPE clock when no PHY is found. This broke both SuperSpeed and USB2 fallback. Move the PHY to the parent usb0 node so the platform driver properly initializes the USB3 PHY and PIPE clock. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
Enable the USB Type-C role switch through the TPS65988 PD controller. The connector node and OF graph were previously guarded behind a preprocessor macro (JUPITER_SDR_USB_ROLE_SW) that was undefined, and the graph endpoint had a wrong remote-endpoint target. Remove the guards, fix the graph link to point to the correct endpoint, and enable usb-role-switch on the DWC3 node so the TPS65988 can drive host/device mode switching. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
A previous patch added documentation for filter_type_available attributes. However, the description for the value attribute (filter_type) was missing. Add documentation for filter_type sysfs ABI. Fixes: 01bb129 ("Documentation: ABI: added filter mode doc in sysfs-bus-iio") Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Reviewed-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/a8dbccac909e8d11e7d47561935a5575b1354d3a.1738680728.git.marcelo.schmitt@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
The ad4130 driver exports in_voltageY-voltageZ_filter_mode and in_voltage-voltage_filter_mode_available attributes to user space. A previous patch merged the documentation for those attributes with the documentation for filter_type/filter_type_available into sysfs-bus-iio. Filter mode and filter type refer to the same feature which is the digital filter applied over ADC samples. However, since datasheets use the term `filter type` and ad4130 driver is the only one using filter_mode, deprecate the filter_mode ABI in favor of filter_type and keep the docs separate to avoid confusion and intricate attribute descriptions. Fixes: 01bb129 ("Documentation: ABI: added filter mode doc in sysfs-bus-iio") Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Reviewed-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/c77b2d65f1115c1c394582f55944d6f685058f9c.1738680728.git.marcelo.schmitt@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add struct axi_adc_info to allow different axi-adc compatibles that can be added to this generic implementation. Signed-off-by: Angelo Dureghello <adureghello@baylibre.com> Link: https://patch.msgid.link/20250210-wip-bl-ad7606_add_backend_sw_mode-v4-4-160df18b1da7@baylibre.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
The Wideband Low Ripple filter is used for AD7768-1 Driver. Document wideband filter option into filter_type_available attribute. Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com> Reviewed-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Link: https://patch.msgid.link/b390ec6d92dd742ace93bd8e40a0df4379b98e23.1741268122.git.Jonathan.Santos@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add backend support for digital filter type selection. This setting can be adjusted within the IP cores interfacing devices. The IP core can be configured based on the state of the actual digital filter configuration of the part. Reviewed-by: Nuno Sá <nuno.sa@analog.com> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Link: https://patch.msgid.link/20250516082630.8236-2-antoniu.miclaus@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add backend support for staring the capture synchronization. When activated, it initates a proccess that aligns the sample's most significant bit (MSB) based solely on the captured data, without considering any other external signals. Reviewed-by: Nuno Sá <nuno.sa@analog.com> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Link: https://patch.msgid.link/20250516082630.8236-3-antoniu.miclaus@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add iio backend support for number of lanes to be enabled. Reviewed-by: Nuno Sá <nuno.sa@analog.com> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Link: https://patch.msgid.link/20250516082630.8236-4-antoniu.miclaus@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add support for enabling/disabling filter based on the filter type provided. This feature is specific to the axi ad408x IP core, therefore add new compatible string and corresponding iio_backend_ops. Reviewed-by: Nuno Sá <nuno.sa@analog.com> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Link: https://patch.msgid.link/20250516082630.8236-6-antoniu.miclaus@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add support for starting the sync process used for data capture alignment. Reviewed-by: Nuno Sá <nuno.sa@analog.com> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Link: https://patch.msgid.link/20250516082630.8236-7-antoniu.miclaus@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add support for setting the number of lanes enabled. Reviewed-by: Nuno Sá <nuno.sa@analog.com> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Link: https://patch.msgid.link/20250516082630.8236-8-antoniu.miclaus@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add devicetree bindings for ad4080 family. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Link: https://patch.msgid.link/20250516082630.8236-9-antoniu.miclaus@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add support for AD4080 high-speed, low noise, low distortion, 20-bit, Easy Drive, successive approximation register (SAR) analog-to-digital converter (ADC). Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Link: https://patch.msgid.link/20250516082630.8236-10-antoniu.miclaus@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add sinc1 and sinc5+pf1 filter types used for ad4080 device. Include these two options into the filter_type available attribute. Add also the option for filter disabled. Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Link: https://patch.msgid.link/20250516082630.8236-11-antoniu.miclaus@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Fix AD4080 chip identification by using the correct 16-bit product ID (0x0050) instead of GENMASK(2, 0). Update the chip reading logic to use regmap_bulk_read to read both PRODUCT_ID_L and PRODUCT_ID_H registers and combine them into a 16-bit value. The original implementation was incorrectly reading only 3 bits, which would not correctly identify the AD4080 chip. Fixes: 6b31ba1 ("iio: adc: ad4080: add driver support") Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Reviewed-by: Nuno Sá <nuno.sa@analog.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Refactor the ad4080 driver to support multiple ADC variants with different resolution bits and LVDS CNV clock count maximums. Changes: - Add lvds_cnv_clk_cnt_max field to chip_info structure - Create AD4080_CHANNEL_DEFINE macro for variable resolution/storage bits - Make LVDS CNV clock count configurable per chip variant - Use chip_info->product_id for chip identification comparison This prepares the infrastructure for adding support for additional ADC parts with different specifications while maintaining backward compatibility with existing AD4080 functionality. Reviewed-by: Nuno Sá <nuno.sa@analog.com> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add device tree binding support for the AD4084 16-bit SAR ADC. Add adi,ad4084 to the compatible enum. A fallback compatible string to adi,ad4080 is not appropriate as the AD4084 has different resolution (16-bit vs 20-bit) and LVDS CNV clock count maximum (2 vs 7), requiring different driver configuration. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add support for AD4084 16-bit SAR ADC. The AD4084 differs from AD4080 in resolution (16-bit vs 20-bit) and LVDS CNV clock count maximum (2 vs 7). Changes: - Add AD4084_CHIP_ID definition (0x0054) - Create ad4084_channel with 16-bit resolution and storage - Add ad4084_chip_info with appropriate configuration - Register AD4084 in device ID and OF match tables Reviewed-by: Nuno Sá <nuno.sa@analog.com> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add device tree binding support for the AD4081 20-bit SAR ADC. Add adi,ad4081 to the compatible enum. A fallback compatible string to adi,ad4080 is not appropriate as the AD4081 has a different LVDS CNV clock count maximum (2 vs 7), requiring different driver configuration. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add support for AD4081 20-bit SAR ADC. The AD4081 has the same resolution as AD4080 (20-bit) but differs in LVDS CNV clock count maximum (2 vs 7). Changes: - Add AD4081_CHIP_ID definition (0x0051) - Create ad4081_channel with 20-bit resolution and 32-bit storage - Add ad4081_chip_info with lvds_cnv_clk_cnt_max = 2 - Register AD4081 in device ID and OF match tables Reviewed-by: Nuno Sá <nuno.sa@analog.com> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add device tree binding support for the AD4083 16-bit SAR ADC. Add adi,ad4083 to the compatible enum. A fallback compatible string to adi,ad4080 is not appropriate as the AD4083 has different resolution (16-bit vs 20-bit) and LVDS CNV clock count maximum (5 vs 7), requiring different driver configuration. Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add support for AD4083 16-bit SAR ADC. The AD4083 differs from AD4080 in resolution (16-bit vs 20-bit) and LVDS CNV clock count maximum (5 vs 7). Changes: - Add AD4083_CHIP_ID definition (0x0053) - Create ad4083_channel with 16-bit resolution and storage - Add ad4083_chip_info with lvds_cnv_clk_cnt_max = 5 - Register AD4083 in device ID and OF match tables Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add device tree binding support for the AD4086 14-bit SAR ADC. Add adi,ad4086 to the compatible enum. A fallback compatible string to adi,ad4080 is not appropriate as the AD4086 has different resolution (14-bit vs 20-bit) and LVDS CNV clock count maximum (4 vs 7), requiring different driver configuration. Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add support for AD4086 14-bit SAR ADC. The AD4086 differs from AD4080 in resolution (14-bit vs 20-bit) and LVDS CNV clock count maximum (4 vs 7). Changes: - Add AD4086_CHIP_ID definition (0x0056) - Create ad4086_channel with 14-bit resolution and 16-bit storage - Add ad4086_chip_info with lvds_cnv_clk_cnt_max = 4 - Register AD4086 in device ID and OF match tables Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add device tree binding support for the AD4087 14-bit SAR ADC. Add adi,ad4087 to the compatible enum. A fallback compatible string to adi,ad4080 is not appropriate as the AD4087 has different resolution (14-bit vs 20-bit) and LVDS CNV clock count maximum (1 vs 7), requiring different driver configuration. Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add support for AD4087 14-bit SAR ADC. The AD4087 differs from AD4080 in resolution (14-bit vs 20-bit) and LVDS CNV clock count maximum (1 vs 7). Changes: - Add AD4087_CHIP_ID definition (0x0057) - Create ad4087_channel with 14-bit resolution and 16-bit storage - Add ad4087_chip_info with lvds_cnv_clk_cnt_max = 1 - Register AD4087 in device ID and OF match tables Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Add imply for AD4080 ADC driver. Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
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-renamed file to fix typo
-added axi_uartlite
-Replaced ifdef statements with if and if !<>
-added a helper funciton to write kHz, GHz, and MHz.
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