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So far, configure inspected the CPU of the build machine and compiled all of msolve with the SIMD extensions found there. Binaries built on a recent machine thus crashed with an illegal instruction on older x86-64 CPUs, and Linux distributions, which must target the baseline architecture, could not ship the vectorized code at all (see algebraic-solving#71). Now, the AVX2 and AVX-512 kernels are always compiled when the compiler supports them, each marked with a function-level target attribute, while the remaining code is compiled for the baseline architecture. The kernel to use is chosen at runtime via __builtin_cpu_supports. The new header src/msolve/cpu_features.h provides the target attributes, the runtime checks and the SIMD intrinsics includes; with e.g. -march=native the checks are resolved at compile time. In neogb, the inline SIMD branches of the row reduction routines are moved into separate scalar/NEON/AVX2/AVX-512 kernels, without changing which instruction sets each routine uses. The fglm kernels already were separate functions and only get the target attributes. configure now only checks whether the compiler can build these kernels and defines HAVE_AVX2_KERNELS and HAVE_AVX512_KERNELS accordingly. AX_EXT and the m4 macros only used by it are removed. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
| * Jérémy Berthomieu | ||
| * Christian Eder | ||
| * Mohab Safey El Din */ |
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| * Jérémy Berthomieu | |
| * Christian Eder | |
| * Mohab Safey El Din */ | |
| * Weijia Wang */ |
(sorry for the previous suggestion, I had not selected the three relevant lines correctly)
Shouldn't this be your name here as this file's author? or keep others if you wish, but at least add yours (in this new file and all other substantially modified files)?
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Ok, I'm just more used to per-file copyright notices, which are usually about the contributors to that specific file. But maybe how to do this is not well stabilized in msolve yet. When I did some substantial work in some FGLM file (linalg-fglm.c), I was advised to add my name to this file's copyright. Don't hesitate to do the same.
To avoid any slowdown when building for one's own machine, don't we want rather that by default "-march=native" is added to CFLAGS (without user intervention)? Or would this maybe break the purpose of this PR? I'm just reacting here because of the observation that "default builds on recent CPUs may be slightly slower there", which is maybe something not wanted... well, this is quantitatively vague, so it depends: if "slightly slower" means "barely noticeable", then fine. |
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I think it's worth running some benchmarks. But indeed, using |
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I think that we need a clear view of the potential slowdown on different platforms before investigating more. The performance loss should clearly be negligeible including on intensive computations |
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IMHO This PR is not the first experiment of this sort, as far as I recall MPIR, an abandoned fork of GMP, was doing a similar thing. Thus, I wonder whether microcode changes might break the code in this PR. If so, it's a non-starter. |
Fixes #71.
So far,
configureinspected the CPU of the build machine (AX_EXT) and compiled all of msolve with the SIMD extensions found there. Binaries built on a recent machine thus crash with an illegal instruction on older x86-64 CPUs, and Linux distributions, which must target the baseline architecture, cannot ship the vectorized code at all.This PR compiles the AVX2 and AVX-512 kernels whenever the compiler supports them and selects them at runtime, so that the same binary runs on every x86-64 CPU and uses the best kernels available.
Changes
src/msolve/cpu_features.h:TARGET_AVX2/TARGET_AVX512function attributes, runtime checkscpu_has_avx2()/cpu_has_avx512()(via__builtin_cpu_supports), and theimmintrin.h/arm_neon.hincludes. If the extensions are enabled globally (e.g.-march=native), the checks are resolved at compile time.neogb: the inline#ifSIMD branches of the row reduction routines inla_ff_8.c,la_ff_16.candla_ff_32.care moved into separate_scalar/_neon/_avx2/_avx512kernels with a small dispatcher. The kernel bodies are unchanged, and each routine keeps using exactly the instruction sets it used before (e.g. the trace/sat/sba routines still only use AVX2). The four identical AVX2 copies of the 31 bit kernel inla_ff_32.cnow share one kernel.fglm: the kernels already were separate functions and only get the target attributes;dense_matrix_vector_product()replaces the compile-time selection.configure.ac:AX_EXTis replaced by link checks whether the compiler can build the kernels, definingHAVE_AVX2_KERNELSandHAVE_AVX512_KERNELS(renamed fromHAVE_AVX2/HAVE_AVX512_Fto make the new meaning explicit).SIMD_FLAGS/CPUEXT_FLAGSand the m4 macros only used byAX_EXTare removed.INSTALL: short note on the runtime selection and on-march=native.Things to be aware of
-march=nativetoCFLAGS. A benchmark on real AVX2/AVX-512 hardware would be welcome.Testing
All 68 tests of
make checkpass on:qemu-x86_64 -cpu Haswell/-cpu max(AVX2 kernels)Additionally, the disassembly of the x86_64 libraries shows AVX registers only inside the kernel functions, and the code compiles without warnings with
-march=x86-64,-march=haswelland-march=skylake-avx512. The AVX-512 kernels could not be exercised at runtime locally (QEMU does not emulate AVX-512).AI disclosure
The changes in this PR were made with the assistance of generative AI (Claude Code), and reviewed by me.
🤖 Generated with Claude Code