Introduction to Computer-aided VLSI Design

[English] | 繁體中文

This repository contains four programming lab assignments for the "Introduction to Computer-aided VLSI Design" course. Below are the topic descriptions and implementation methods for each lab.

Lab 1: Test Pattern Generation

Topic Description

Write a program to find the minimum set of test patterns (Minimum Test Pattern Set) capable of detecting all Stuck-At Faults (including Stuck-At-0 and Stuck-At-1) for a specific logic circuit.

Implementation Method

Implemented using C++ with a Greedy Algorithm.

1. First, simulate the circuit with all 16 different input vectors (from 0 to 15), recording which nodes' Stuck-At faults can be detected by each input (building a Fault Dictionary).
2. Using a greedy strategy, iteratively select the input vector that covers the "maximum number of currently undetected faults."
3. Repeat this process until all Stuck-At Faults are covered, thereby obtaining the optimal Minimum Test Pattern Set.

---

Lab 2: Scheduling

Topic Description

Implement the List Scheduling algorithm used in High-Level Synthesis (HLS) using C/C++. The program must be able to read given Data Flow Graphs (including DFG1, DFG2, and an RGB to YUV DFG) and perform scheduling under specified computational resource constraints (e.g., specific numbers of adders and multipliers).

Implementation Method

Wrote the List Scheduling program using C++.

1. The program reads the DFG nodes (Operations) and dependencies from a text file.
2. Uses Depth-First Search (DFS) to calculate the Critical Path Priority for each node (the longest path to the output; the longer the path, the higher the priority).
3. In each Cycle, places all nodes whose dependencies are satisfied (Ready) into a Ready Queue, and sorts them according to Priority.
4. Based on the currently available ALU resources (number of Multipliers and Adders), preferentially schedules operations with the highest Priority, completing Resource-Constrained Scheduling.

---

Lab 3: RTL Design of RGB to YUV

Topic Description

Implement the Register Transfer Level (RTL) design of an RGB to YUV conversion circuit using Verilog HDL. The design must be divided into a Datapath and a Controller (Finite State Machine), and its functionality must be verified using Synopsys VCS and Verdi with a provided Testbench.

Implementation Method

Based on the scheduling and resource allocation results from Lab 2, used a Structural Design approach for hardware description:

1. Datapath: Wrote individual sub-modules, including Multipliper.v, Add.v, MUX2.v, MUX3.v, MUX4.v, Register.v, and ROM.v, instantiated them in Datapath.v, and wired them together.
2. Controller: Implemented a Finite State Machine (FSM) in Controller.v, outputting corresponding Control Signals (such as MUX selection signals, Register Load signals) based on the current state to control the computation flow in the Datapath.
3. Integrated everything into a top-level module in RGB2YUV.v, and performed verification by reading an image through the Testbench.

---

Lab 4: Logic Synthesis of RGB to YUV

Topic Description

Perform Logic Synthesis on the Lab 3 RGB to YUV RTL circuit using Synopsys Design Compiler (DC). Two architectures need to be synthesized separately:

• Version 1: Uses 1 Multiplier and 1 Adder.
• Version 2: Uses 3 Multipliers and 3 Adders.

Therefore, the scheduling results from Lab 2 are also required. Finally, compare the Timing, Area, Power, and the number of execution Cycles spent on both versions.

Implementation Method

Wrote TCL scripts to specify the synthesis constraints (Constraints, SDC), and used Design Compiler to convert the RTL code into a Gate-level Netlist:

1. Setup and synthesized both Version 1 (fewer resources, requires more Cycles to finish calculating one Pixel) and Version 2 (more resources, fewer computation Cycles).
2. Analyzed the PPA (Power, Performance, Area) trade-offs between the two architectures using the Reports generated by Design Compiler.
3. Compiled and compared the differences in hardware costs and computational efficiency between the resource-constrained architecture (Version 1) and the highly parallel architecture (Version 2), summarizing them in the lab report.