GitHub - RijulChaddha9504/ECE124StateMachineLab: State Machines

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
.qsys_edit		.qsys_edit
db		db
incremental_db		incremental_db
output_files		output_files
simulation		simulation
LogicalStep_Lab4.qpf		LogicalStep_Lab4.qpf
LogicalStep_Lab4.tcl		LogicalStep_Lab4.tcl
LogicalStep_Lab4_top.qsf		LogicalStep_Lab4_top.qsf
LogicalStep_Lab4_top.qws		LogicalStep_Lab4_top.qws
LogicalStep_Lab4_top.vhd		LogicalStep_Lab4_top.vhd
LogicalStep_Lab4_top.vhd.bak		LogicalStep_Lab4_top.vhd.bak
LogicalStep_Lab4_top_assignment_defaults.qdf		LogicalStep_Lab4_top_assignment_defaults.qdf
PB_filters.vhd		PB_filters.vhd
PB_inverters.vhd		PB_inverters.vhd
State_Machine_Example.vhd		State_Machine_Example.vhd
State_Machine_RG.vhd.bak		State_Machine_RG.vhd.bak
State_Machine_RYG.vhd		State_Machine_RYG.vhd
State_Machine_RYG.vhd.bak		State_Machine_RYG.vhd.bak
Waveform.vwf		Waveform.vwf
Waveform1.vwf		Waveform1.vwf
Waveform2.vwf		Waveform2.vwf
Waveform3.vwf		Waveform3.vwf
Waveform4.vwf		Waveform4.vwf
Waveform5.vwf		Waveform5.vwf
Waveform6.vwf		Waveform6.vwf
Waveform8 - Copy.vwf		Waveform8 - Copy.vwf
Waveform8.vwf		Waveform8.vwf
Waveform9.vwf		Waveform9.vwf
clock_generator.vhd		clock_generator.vhd
clock_generator.vhd.bak		clock_generator.vhd.bak
holding_register.vhd		holding_register.vhd
holding_register.vhd.bak		holding_register.vhd.bak
pb_filters.vhd.bak		pb_filters.vhd.bak
pb_inverters.vhd.bak		pb_inverters.vhd.bak
segment7_mux.vhd		segment7_mux.vhd
synchronizer.vhd		synchronizer.vhd
synchronizer.vhd.bak		synchronizer.vhd.bak