PANDA

PANDA is an LLM-enhanced, performance-driven analog design framework that bridges high-level design intent and final layout generation. It actively manages cross-stage dependencies through guided topology synthesis, substructure-aware sizing, and constraint-driven layout generation, shifting analog design automation from isolated algorithm-centric execution to intent-centric co-design. The repository provides a reproducible implementation that connects topology generation, sizing, Spectre simulation, placement, routing, LVS, PEX, and post-layout feedback through explicit task contracts and isolated run directories.

This repository intentionally separates reusable flow code from private EDA state. Cadence, PDK, Calibre, OpenAccess databases, Paprika binaries, and generated GDS/PEX artifacts are not tracked.

Current Status

The project has two real, non-smoke flows that should be used as the reference cases.

Case	Status	Current result
Three-stage high-gain OTA	Topology, real Spectre sizing, true-PCell placement/routing, layout-matched LVS/PEX, and post-PEX Spectre completed on the configured Linux EDA host	Post-PEX layout-matched gain 74.25 dB, UGBW 1.49 MHz, phase margin 98.10 deg, current 14.84 uA
StrongARM / SA comparator	Topology, real transient Spectre sizing, flattened T65 PCell GDS export, placement, and routing completed on the configured Linux EDA host	Delay about 155 ps to abs(VOUTP - VOUTN)=0.6 V, about 190 ps to 1.0 V, energy about 125 fJ/decision

Important caveats:

• Smoke adapters are only orchestration checks. Do not report smoke output as a design result.
• The OTA result above is layout-matched PEX. Topology-source exact LVS is still blocked by the MP_STAGE3_LOAD PCell property-expression mismatch.
• Older OTA phase-margin values above 170 deg are invalid historical output. The corrected try17 values are about 99.31 deg pre-layout and 98.10 deg post-PEX.
• Placement/routing return code 0 is not enough. The route log must also be clean of FAILED WITH DRC, failed at, and similar fatal markers.

See docs/panda_real_chain_repro.md and docs/panda_real_chain_buglog_20260517.md for the detailed run history and failure analysis.

Run PANDA

1. Clone and prepare binaries

git clone https://github.com/PKU-IDEA/PANDA.git
cd PANDA
git lfs pull
python3 -m venv .venv
. .venv/bin/activate
python3 -m pip install -U pip
python3 -m pip install -r requirements.txt
python3 -m compileall analog_agent_flow.py analogxpert simulation sizing virtuoso_run \
  virtuoso-bridge-lite-main/src virtuoso-bridge-lite-main/autopr_skill

git lfs pull is required for the released placement/routing kernel binaries under pr_kernel/.

The optional Virtuoso bridge is an installable Python package. Install it on a machine that can reach the EDA host:

python3 -m pip install -e virtuoso-bridge-lite-main

For the full dependency matrix, including Spectre, Virtuoso, PCell GDS, placement/routing kernels, and LVS/PEX wrappers, read docs/runtime_dependencies.md.

The placement/routing binaries also need non-Python shared libraries. Check pr_kernel/README.md before running real P&R.

2. Dependency checklist

Python-side dependencies are installed with:

python3 -m pip install -r requirements.txt
python3 -m pip install -e virtuoso-bridge-lite-main

requirements.txt currently contains:

Package	Used for
numpy	Sizing vectors, metrics, numeric utilities
scipy	Differential-evolution sizing and statistics
scikit-learn	Additive Gaussian-process sizing helper
openai	AnalogXpert-compatible topology LLM calls
pydantic	Virtuoso bridge data models
PyYAML	Virtuoso bridge schematic parameter-filter parsing
python-dotenv	Optional .env loading for local bridge profiles

The following system tools are expected on the machine that runs PANDA:

Tool	Required for
git and git-lfs	Repository checkout and P&R binary download
Python >=3.9	PANDA orchestration and bridge package
bash	Placement/routing shell adapters
OpenSSH client	Remote Virtuoso/Spectre bridge flows
file, ldd, readelf, sha256sum or shasum	P&R binary dependency audit on Linux
Cadence Virtuoso and Spectre	Real PCell generation, sizing, and simulation
PDK model files, stream-out layer map, PR tech/stdcell JSON, flattened PCell GDS	Real sizing and placement/routing
LVS/PEX tool wrappers such as Calibre adapters	Layout verification, RC extraction, and post-layout simulation

The released placement/routing binaries are Linux x86-64 ELF executables. The direct dynamic libraries audited from both pr_kernel/placement and pr_kernel/routing are:

libz.so.1
libtorch.so
libtorch_cpu.so
libc10.so
libpthread.so.0
libstdc++.so.6
libm.so.6
libgcc_s.so.1
libc.so.6
ld-linux-x86-64.so.2

Required symbol versions:

GLIBC_2.14
GLIBCXX_3.4.26
CXXABI_1.3.5

In practice, put the non-system P&R runtime libraries in one directory:

$PANDA_REPO/pr_kernel/libso/
|-- libc10.so
|-- libtorch.so
|-- libtorch_cpu.so
`-- libstdc++.so.6        # needed if the host system libstdc++ is too old

Then configure:

export PR_LIB_DIR="$PANDA_REPO/pr_kernel/libso"
export LD_LIBRARY_PATH="$PR_LIB_DIR:${LD_LIBRARY_PATH:-}"

On the Linux EDA host, validate the binaries before real placement/routing:

bash pr_kernel/check_deps.sh

The dependency audit used these checks: file for binary type, readelf -d for direct NEEDED libraries, readelf --version-info for GLIBC/GLIBCXX requirements, ldd for resolved or missing runtime libraries, and SHA-256 hashes for the two released binaries. A usable P&R environment has no not found entries and no GLIBCXX_* not found or GLIBC_* not found errors.

3. Run the local smoke check

Use smoke mode first to verify Python imports, task contracts, artifact paths, and placement/routing wrapper wiring:

python3 virtuoso_run/run_demo.py --demo all --backend smoke \
  --run-root run/virtuoso/smoke_check

Smoke mode uses seed sizing and placeholder placement/routing adapters. It is not a real circuit result and must not be reported as topology, sizing, layout, or post-layout performance.

4. Configure a real EDA environment

Real PANDA runs require user-provided access to Spectre, Virtuoso, licensed PDK models, flattened PCell GDS, and PR technology inputs. Copy the example env file and fill only local private paths:

mkdir -p .local/virtuoso_run
cp virtuoso_run/env.real.example .local/virtuoso_run/real.env
${EDITOR:-vi} .local/virtuoso_run/real.env

At minimum, real placement/routing runs need:

export PANDA_REPO=$PWD
export SPECTRE_BIN=/path/to/spectre
export PDK_MODEL_INCLUDE=/path/to/model.scs
export PLACE_KERNEL_BIN=$PWD/pr_kernel/placement
export ROUTE_KERNEL_BIN=$PWD/pr_kernel/routing
export PR_LIB_DIR=$PWD/pr_kernel/libso
export LD_LIBRARY_PATH=$PR_LIB_DIR:${LD_LIBRARY_PATH:-}
export PLACE_TECHFILE=/path/to/lef.json
export PLACE_STDCELL=/path/to/stdcell.json
export PCELL_SKILL_TEMPLATE=$PWD/virtuoso-bridge-lite-main/autopr_skill/pcell_extract/pcell_skill_header.txt
export PANDA_PCELL_GDS_DIR=/path/to/flattened_pcell_gds

PR_LIB_DIR must contain the P&R binary shared libraries described in pr_kernel/README.md, especially the LibTorch CPU runtime and a libstdc++.so.6 new enough for GLIBCXX_3.4.26 on older hosts.

Private env files, PDK content, GDS outputs, OA databases, Calibre outputs, and Spectre PSF directories are intentionally ignored by Git.

5. Run the real demo flows

Three-stage OTA target75:

set -a
. .local/virtuoso_run/real.env
set +a
python3 virtuoso_run/scripts/run_three_stage_ota_target75.py \
  --run-root run/virtuoso/three_stage_ota_target75_demo

StrongARM comparator:

set -a
. .local/virtuoso_run/real.env
set +a
python3 virtuoso_run/scripts/run_sa_comp_panda_236.py \
  --run-root run/virtuoso/sa_comp_demo

Expected checkpoint artifacts are written inside the selected run root:

<run-root>/
|-- design_request.json
|-- run_manifest.json
|-- pcell_gds_flat/
`-- <case>/try1/
    |-- topology_clean.sp
    |-- sizing.json
    |-- sizing_tb.scs
    |-- sizing_parameter_map.json
    |-- placement_result/*.gds
    `-- route_result/*.gds

Always inspect run_route.log for fatal markers such as FAILED WITH DRC even when a wrapper returns success.

6. Build a sizing template for a new topology

sizing/topology_sizing_template.py is the template for new sizing cases. It consumes a PANDA topology artifact and emits a parameterized Spectre deck and parameter map:

python3 sizing/topology_sizing_template.py \
  --run-dir run/sizing_template_try1 \
  --topology-json run/virtuoso/three_stage_ota_target75_demo/three_stage_ota/try1/topology.json \
  --model-include "$PDK_MODEL_INCLUDE" \
  --model-section "${SIZING_MODEL_SECTION:-tt_lib}"

For end-to-end flow runs, set a sizing backend command. The released single point Spectre adapter is useful for validating generated decks; production optimization can replace it with a MOSTAR-compatible wrapper that writes SIZING_BACKEND_RESULT_JSON or SIZING_OPTIMIZED_CSV.

export SIZING_BACKEND_CMD="python3 $PWD/sizing/spectre_backend.py"

License

PANDA uses a dual-license policy:

• Academic and other non-commercial use is permitted under the PolyForm Noncommercial License 1.0.0.
• Commercial use requires a separate written commercial license from the PANDA rights holders. See COMMERCIAL-LICENSE.md. To request a commercial license, contact yibolin@pku.edu.cn. (the commercial license is still free, but simply needs additional application process with the applicant's name and affiliation)

Because commercial use is restricted, this public license is a source-available non-commercial license rather than an OSI open-source license.

All copies, modified versions, redistributions, public demos, benchmark artifacts, technical reports, and derivative works that include or use PANDA must retain the required PANDA notice in NOTICE:

Required Notice: This work uses PANDA, developed by PKU-IDEA and PANDA contributors.

Academic publications, benchmarks, technical reports, and public presentations that use PANDA or results generated by PANDA must acknowledge PANDA and cite the relevant papers listed in the Citation section below.

This repository does not grant rights to third-party proprietary EDA tools, PDKs, foundry data, model files, technology files, generated layouts, signoff decks, or other third-party artifacts.

Citation

If you use this repository, please acknowledge PANDA and cite the relevant papers for the framework and the stage-specific engines you use. The BibTeX entries below cover the framework and each stage-specific engine.

For the full PANDA framework:

@inproceedings{zhang2026panda,
  title     = {{PANDA}: An {LLM}-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation},
  author    = {Haoyi Zhang, Weijian Fan, Xiaohan Gao, Bingyang Liu, Runsheng Wang, and Yibo Lin},
  booktitle = {Proceedings of the 63rd ACM/IEEE Design Automation Conference (DAC)},
  year      = {2026},
  address   = {Long Beach, CA, USA},
  note      = {Invited Paper}
}

For the stage-specific engines used by PANDA:

@inproceedings{zhang2025analogxpert,
  title     = {{AnalogXpert}: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models},
  author    = {Haoyi Zhang, Shizhao Sun, Yibo Lin, Runsheng Wang, Jiang Bian},
  booktitle = {International Symposium of EDA (ISEDA)},
  year      = {2025}
}

@inproceedings{fan2026mostar,
  title     = {{MOSTAR}: Multi-Stage Hierarchical Bayesian Optimization for Substructure-Aware High-Dimensional Analog Circuit Sizing},
  author    = {Weijian Fan, Haoyi Zhang, Weibin Lin, Runsheng Wang, Yibo Lin},
  booktitle = {Asia and South Pacific Design Automation Conference (ASP-DAC)},
  year      = {2026}
}

@inproceedings{zhang2024jointplacement,
  title     = {Joint Placement Optimization for Hierarchical Analog/Mixed-Signal Circuits},
  author    = {Xiaohan Gao, Haoyi Zhang, Bingyang Liu, Yibo Lin, Runsheng Wang, Ru Huang},
  booktitle = {ACM/IEEE International Conference on Computer-Aided Design (ICCAD)},
  year      = {2024}
}

@inproceedings{zhang2023sageroute,
  title     = {{SAGERoute}: Synergistic Analog Routing Considering Geometric and Electrical Constraints},
  author    = {Haoyi Zhang, Xiaohan Gao, Haoyang Luo, Jiahao Song, Xiyuan Tang, Junhua Liu, Yibo Lin, Runsheng Wang, Ru Huang},
  booktitle = {Design, Automation and Test in Europe Conference (DATE)},
  year      = {2023},
  note      = {Best Paper Award}
}

Repository Layout

.
|-- analog_agent_flow.py          # Main task orchestrator and local MCP-style server
|-- flow_request.json             # Default autonomous-flow request
|-- analogxpert/                  # Local topology templates and topology helpers
|-- sizing/                       # Reusable topology-driven sizing template, optimizer glue, and backend adapters
|-- simulation/                   # Spectre deck builder and launcher wrappers
|-- virtuoso-bridge-lite-main/    # Virtuoso/Spectre bridge and PCell GDS export templates
|-- place.py / route.py           # Placement and routing wrapper logic
|-- run_placement.sh              # Placement kernel adapter
|-- run_route.sh                  # Routing kernel adapter
|-- verification.py               # LVS/PEX backend wrapper contracts
|-- virtuoso_run/                 # Isolated real/demo run harnesses
|-- task_skills/                  # Per-task skill contracts for the PANDA stages
|-- agent_skills/                 # Main-agent skill backup for real configured Linux EDA host flows
|-- docs/                         # Contracts, status notes, repro notes, buglogs
|-- template_json/                # allconfig templates and PR inputs
`-- topology_gen/                 # Legacy topology-generation tools and fallback scripts

Generated data should stay under ignored paths such as run/, outputs/, and run_artifacts/.

Flow Model

The main flow is a sequence of explicit tasks. Each task receives structured inputs, writes artifacts to the current attempt directory, and returns a JSON status object.

1. topology_generation
2. post_topology_decision
3. sizing
4. simulator_launch
5. placement_pr_planning
6. placement
7. routing_pr_planning
8. routing
9. lvs
10. pex

Before sizing starts, the flow must carry matched-device relationships from post-topology planning into downstream_inputs.sizing.symmetry_constraints. Differential pairs, current mirrors, active loads, and matched capacitors or resistors should be tied to shared sizing variables or explicit ratio constraints before the optimizer runs. The same relationships should stay consistent with placement/routing symmetry groups.

The implementation uses an MCP-style local interface in analog_agent_flow.py. The stable methods are:

Method	Purpose
analog.topology.generate	Generate or load topology netlists
analog.post_topology.plan	Plan downstream constraints after topology
analog.sizing.optimize	Build sizing decks, apply sizing symmetry constraints, and call a real sizing backend
analog.simulator.launch	Build and optionally launch Spectre decks
analog.placement_pr.plan	Build placement constraints
analog.placement.execute	Run placement through place.py and run_placement.sh
analog.routing_pr.plan	Build routing constraints
analog.routing.execute	Run routing through route.py and run_route.sh
analog.lvs.run	Run configured LVS backend
analog.pex.extract	Run configured PEX backend

For the full interface contract, read docs/mcp_contract.md.

Real EDA Host Flows

The real-chain demos run on a configured Linux EDA host that has access to Virtuoso, Spectre, the PDK, and the Paprika placement/routing binaries. If your EDA host is behind a gateway, connect through your own private SSH chain:

ssh -o BatchMode=yes -o ConnectTimeout=10 <gateway-user>@<gateway-host> \
  'ssh -o BatchMode=yes -o ConnectTimeout=10 <eda-user>@<eda-host> "hostname"'

Important private paths are supplied through environment variables, usually by copying virtuoso_run/env.real.example into .local/virtuoso_run/real.env and filling it locally:

Item	Path
Repo	$PANDA_REPO
Optional flow copy	$PANDA_FLOW_ROOT
Virtuoso workspace	$VIRTUOSO_WORKSPACE
Virtuoso wrapper	$VIRTUOSO_BIN
Spectre	$SPECTRE_BIN
T65 model	$PDK_MODEL_INCLUDE
PR placement binary	$PANDA_REPO/pr_kernel/placement
PR routing binary	$PANDA_REPO/pr_kernel/routing
PR shared libraries	$PANDA_REPO/pr_kernel/libso

The placement and routing kernel binaries are stored with Git LFS. After cloning, run git lfs pull before launching real P&R. Then run bash pr_kernel/check_deps.sh on the Linux EDA host and fix any missing dynamic libraries before starting placement/routing.

Reproduce the StrongARM comparator

This case reproduces the StrongARM / SA comparator flow from design intent to transient sizing, true PCell GDS export, placement, and routing. It is the recommended comparator demo for checking the non-smoke PANDA path on a configured Linux EDA host.

Design intent: generate a StrongARM latch comparator for low-energy transient decision evaluation, then verify delay and switching energy with real Spectre transient simulation before taking the topology through true-PCell placement and routing.

Before running, fill .local/virtuoso_run/real.env with the private Spectre, Virtuoso, PDK, PCell, and P&R paths, then validate the P&R runtime:

bash pr_kernel/check_deps.sh

Run the case in a fresh isolated directory:

cd $PANDA_REPO
set -a
. .local/virtuoso_run/real.env
set +a
python3 virtuoso_run/scripts/run_sa_comp_panda_236.py \
  --run-root run/virtuoso/real_chain_sa_comp_<tag>

The runner executes the case-specific stages in order:

1. Generate the STRONGARM_COMP topology.
2. Run real Spectre transient sizing through virtuoso_run/scripts/strongarm_sizing_backend.py.
3. Export flattened MOS PCell GDS through Virtuoso.
4. Run Paprika placement.
5. Run Paprika routing and inspect the route log.

Expected output layout:

Stage	Main artifact
Topology	comparator/try1/topology_clean.sp
Sizing	comparator/try1/sizing.json, comparator/try1/strongarm_tran_tb.scs, comparator/try1/strongarm_tran.raw/
PCell GDS	<run-root>/pcell_gds_flat/*.gds
Placement	comparator/try1/placement_result/STRONGARM_COMP.gp.gds
Routing	comparator/try1/route_result/STRONGARM_COMP.route.gds, comparator/try1/route_result/route_wires.json

Parse transient metrics from the generated Spectre raw directory:

python3 virtuoso_run/scripts/extract_strongarm_perf.py \
  run/virtuoso/real_chain_sa_comp_<tag>/comparator/try1/strongarm_tran.raw

Reference accepted metrics from the known-good try4 run:

Metric	Value
Delay to abs(VOUTP - VOUTN)=0.6 V	about 155 ps
Delay to abs(VOUTP - VOUTN)=1.0 V	about 190 ps
Energy	about 125 fJ/decision

Known-good run root:

$PANDA_REPO/run/virtuoso/real_chain_20260521_panda_sa_comp_full_try4/comparator/try1

Accept routing only after checking the route log, not just the return code:

grep -n 'FAILED WITH DRC\|failed at\|terminate called\|std::out_of_range' \
  run/virtuoso/real_chain_sa_comp_<tag>/comparator/try1/run_route.log

Reproduce or inspect the high-gain OTA

This case reproduces the high-gain three-stage OTA target75 demo for sensor readout: differential input, single-ended output, target gain around 75 dB, and target UGBW around 1 MHz. The public runner covers topology generation, real Spectre sizing, pre-layout deck generation, true-PCell placement, and routing. The layout-matched LVS/PEX metrics below come from the accepted try17 post-layout run.

Design intent: design a three-stage OTA with differential input and single output for sensor readout, targeting high open-loop gain and robust phase margin near a 1 MHz unity-gain bandwidth.

Before running, configure .local/virtuoso_run/real.env and verify the P&R runtime in the same way as the comparator case:

bash pr_kernel/check_deps.sh

Run the OTA case in a fresh isolated directory:

cd $PANDA_REPO
set -a
. .local/virtuoso_run/real.env
set +a
python3 virtuoso_run/scripts/run_three_stage_ota_target75.py \
  --run-root run/virtuoso/three_stage_ota_target75_<tag>

The runner executes the case-specific stages in order:

1. Generate the THREE_STAGE_OTA_HG topology.
2. Inject the target75 operating assumptions for T65: VDD=1.2, VCM=600m, VBN=0.62, VBP2=0.52, VBP3=0.64, and CLOAD=500f.
3. Run real Spectre sizing.
4. Generate the pre-layout simulation deck.
5. Run Paprika placement.
6. Run Paprika routing and inspect the route log.

Expected output layout:

Stage	Main artifact
Topology	three_stage_ota/try1/topology_clean.sp
Sizing	three_stage_ota/try1/sizing.json, three_stage_ota/try1/sizing_tb.scs, three_stage_ota/try1/sizing_parameter_map.json
Placement	three_stage_ota/try1/placement_result/THREE_STAGE_OTA_HG.gp.gds
Routing	three_stage_ota/try1/route_result/THREE_STAGE_OTA_HG.route.gds
Run manifest	<run-root>/run_manifest.json

Generated GDS stays under run/ and is ignored by Git.

Reference run roots:

# Full topology/sizing/placement/routing run
$PANDA_REPO/run/virtuoso/real_chain_20260518_panda_direct_true_pcell_try17_full_stage3_w32m2/three_stage_ota/try1

# Layout-matched LVS/PEX and post-PEX run
$PANDA_REPO/run/virtuoso/real_chain_20260518_panda_direct_true_post_layout_try17_layoutmatched_lvs_pex

Corrected accepted metrics:

Stage	Gain	UGBW	Phase margin	Current
Pre-layout try17	80.05 dB	1.89 MHz	99.31 deg	16.89 uA
Post-PEX layout-matched try17	74.25 dB	1.49 MHz	98.10 deg	14.84 uA

Accept routing only after checking the route log, not just the return code:

grep -n 'FAILED WITH DRC\|failed at\|terminate called\|std::out_of_range' \
  run/virtuoso/three_stage_ota_target75_<tag>/three_stage_ota/try1/run_route.log

Known scope caveat: the post-PEX result is layout-matched. Topology-source exact LVS is still blocked by the MP_STAGE3_LOAD PCell property-expression mismatch documented in docs/panda_real_chain_buglog_20260517.md.

Environment Variables

The flow is intentionally adapter-driven. Configure real tools through environment variables instead of hardcoding private paths.

Variable	Purpose
ANALOG_AGENT_RUN_ROOT	Root directory for attempts, default run
TOPOLOGY_BACKEND	local, codex, or legacy external topology behavior
TOPOLOGY_CANDIDATE_PATH	Explicit topology candidate netlist
SIZING_BACKEND_CMD	Real sizing backend command
SIZING_BACKEND	Built-in sizing mode selector, for example builtin
SPECTRE_BIN / SPECTRE_CMD	Spectre executable or launch command
PLACE_KERNEL_BIN	Placement binary path
ROUTE_KERNEL_BIN	Routing binary path
PR_KERNEL_BIN	Shared fallback PR binary path
LD_LIBRARY_PATH	Must include PR shared libraries for Paprika kernels
PLACE_TECHFILE / ROUTE_TECHFILE	PR technology input
PLACE_STDCELL / ROUTE_STDCELL	PR standard-cell input
PLACE_PCELLDIR / ROUTE_PCELLDIR	Flattened PCell GDS directory
ALLCONFIG_TEMPLATE_PATH	allconfig.json template override
LVS_CMD	Real LVS backend command
PEX_CMD	Real PEX backend command

For backend details, read docs/backend_adapters.md.

Artifacts

Each attempt directory is self-contained. Typical files include:

try1/
|-- topology.json
|-- topology_clean.sp
|-- post_topology_decision.json
|-- sizing.json
|-- sizing_tb.scs
|-- sizing_parameter_map.json
|-- pre_sim_tb.scs
|-- post_sim_tb.scs
|-- placement_pr.json
|-- place_input.json
|-- pl.json
|-- routing_pr.json
|-- route_input.json
|-- rt.json
|-- allconfig.json
|-- multi_symmetric_group.json
|-- lvs.json
|-- pex.json
`-- post_layout_pex.scs

For real Paprika runs, the meaningful layout deliverables are usually under placement_result/ and route_result/. The wrapper files pl.bin and rt.bin can be zero-byte placeholders and should not be treated as the final GDS.

Main-Agent Skill

The real PANDA/Virtuoso debugging workflow is captured as a Codex skill:

agent_skills/panda-virtuoso-flow/

A local installed copy may also live at:

~/.codex/skills/panda-virtuoso-flow/

Use this skill whenever the task mentions:

• real PANDA reruns on the configured Linux EDA host
• three-stage OTA try17 status
• StrongARM / SA comparator reproduction
• true PCell GDS generation
• placement/routing kernel failures
• LVS/PEX/post-PEX status

Debug Rules Learned

• Keep every rerun in a new isolated directory.
• Stop at the first failing checkpoint and identify the concrete bad input, script, or tool log.
• Use the Cadence wrapper $VIRTUOSO_BIN; do not call the 64bit/virtuoso binary directly in non-interactive SSH.
• For configured Linux EDA host Python 3.6 flow copies, avoid from __future__ import annotations and A | B typing syntax.
• Use fixed capacitor types for layout input. The working T65 path uses a flattened fixed crtmom GDS with explicit PLUS/MINUS/BULK text.
• Resistor PCell GDS must include PLUS/MINUS text on the M1 pin rectangles.
• StrongARM Spectre decks should use explicit DC parameters such as VINPDC=605m and VINNDC=595m; Spectre 19.1 rejects expressions like dc='VCM+VDIFF/2'.
• Avoid multi-underscore MOS aliases in Paprika PCell names. Generate both the original and stripped GDS aliases when needed.
• Check route logs for fatal text even when the wrapper returns success.
• Treat any post-layout result generated before clean LVS as diagnostic only.

Development Notes

Use rg and the docs under docs/ first when debugging old runs. The most useful starting points are:

• docs/panda_real_chain_repro.md
• docs/panda_real_chain_buglog_20260517.md
• docs/mcp_contract.md
• docs/skill_mcp_standard.md
• virtuoso_run/README.md

Before committing, keep generated private artifacts out of Git. The repository should contain reproducible scripts, contracts, and documentation, not PDK or EDA output databases.