Add minimal SoC with ALU and memory for classification

[MelkorBalrog]

Summary

• Introduce alu.v implementing add/sub/logic ops and status flags for CPU use.
• Add simple_ram.v providing synchronous RAM for instruction and data storage.
• Build soc.v top-level that integrates a tiny CPU, ALU, RAM, and the existing transformer classifier with a sample program.

Testing

• iverilog hdl/soc.v hdl/alu.v hdl/simple_ram.v hdl/transformer_classifier.v hdl/classification_asm.v -o /tmp/soc.out (fails: command not found)
• python -m py_compile $(git ls-files '*.py')

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https://chatgpt.com/codex/tasks/task_b_688f83ae5e7083278a7f94289e0f0723