Add RISC-V vector spec v1.0 support (new submission)#408
Open
sh-zheng wants to merge 3 commits into
Open
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Hi dear developers,
This is a subsequent work of PR #279 , which is too old to merge.
Enable rvv 1.0 with --enable-rvv.
Correctness tests for FP32 and FP64 are done with bench --verify on qemu, with vlen=128, 256, 512 and 1024.
The original kernel is based on @rdolbeau 's work, with some optimizations:
a. Support vlen from 128 to 65536.
b. Generate VTW1, VTW2, and VTWS with C micro, instead of extra C files.
c. During the computation, adopt vslide1up/down.vx instead of vrgather, and remove the mask operations, which may improve the performance.