[bebop/rushb] Fix bugs in rushB mode to run E2E models

.github/workflows/check.yaml

@@ -63,12 +63,12 @@ jobs:
       matrix:
         include:
           - chip: toy
-            enable_rushb: false
+            enable_rushb: true
             run_bemu_elf_tests: true
             run_bemu_pk_tests: true
             run_verilator_batch_tests: true
           - chip: pebble
-            enable_rushb: false
+            enable_rushb: true
             run_bemu_elf_tests: true
             run_bemu_pk_tests: true
             run_verilator_batch_tests: true
@@ -164,6 +164,9 @@ jobs:
           nix develop -c bbdev workload --build '--chip ${{ matrix.chip }} --rushB bemu'
           nix develop -c bbdev bebop-bemu --batch '--chip ${{ matrix.chip }} --test elf-tests --rushB --clean-before'
           nix develop -c bbdev bebop-bemu --batch '--chip ${{ matrix.chip }} --test pk-tests --rushB --clean-before'
+          nix develop -c bbdev bebop-verilator --clean '--chip ${{ matrix.chip }} --rushB'
+          nix develop -c bbdev bebop-verilator --verilog '--chip ${{ matrix.chip }} --rushB'
+          nix develop -c bbdev bebop-verilator --build '--jobs 16 --chip ${{ matrix.chip }} --rushB'
           nix develop -c bbdev workload --build '--chip ${{ matrix.chip }} --rushB verilator'
           nix develop -c bbdev bebop-verilator --batch '--chip ${{ matrix.chip }} --test elf-tests --rushB --clean-before'
           nix develop -c bbdev bebop-verilator --batch '--chip ${{ matrix.chip }} --test pk-tests --rushB --clean-before'

arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala

@@ -163,7 +163,8 @@ class GlobalROB(val b: GlobalConfig) extends Module {
   }
   val hasCommit = commitScan.asUInt.orR
   val tailAlias = Wire(UInt(b.frontend.bank_id_len.W))
-  tailAlias := (b.frontend.vbank_id_upper_bound + 1).U + tailPtr
+  tailAlias :=
+    (b.frontend.vbank_id_upper_bound + 1).U(b.frontend.bank_id_len.W) + tailPtr
 
   val tailAliasLive = WireDefault(false.B)
   for (i <- 0 until robDepth) {

arch/src/main/scala/framework/frontend/globalrs/GlobalScheduler.scala

@@ -228,5 +228,5 @@ class GlobalScheduler(val b: GlobalConfig) extends Module {
   io.scheduler_rocc_o.resp.bits.rd   := 0.U
   io.scheduler_rocc_o.resp.bits.data := 0.U
   io.scheduler_rocc_o.busy           := rob.io.full || fenceActive || barrierWaitROB || barrierWaitRelease
-  io.retired                         := rob.io.complete.fire
+  io.retired                         := rob.io.complete.fire && rob.io.entry_valid(rob.io.complete.bits)
 }

arch/src/main/scala/framework/system/core/accelerator/BuckyballAccelerator.scala

@@ -172,7 +172,15 @@ class BuckyballAccelerator(val b: GlobalConfig)(edge: TLEdgeOut) extends Module
   io.interrupt := memDomain.io.tlbExp(0).interrupt
 
   // --- Busy watchdog ---
-  val busy_counter = RegInit(0.U(32.W))
-  busy_counter := Mux(frontend.io.busy, busy_counter + 1.U, 0.U)
-  assert(busy_counter < 100000.U, "BuckyballAccelerator: busy for too long!")
+  // BootRom clears and initializes the local memories before the external
+  // command interface becomes ready. That initialization can legitimately
+  // exceed the runtime watchdog limit, so only start monitoring after the
+  // first external command has handshaken.
+  val runtime_started = RegInit(false.B)
+  when(io.cmd.fire) {
+    runtime_started := true.B
+  }
+  val busy_counter    = RegInit(0.U(32.W))
+  busy_counter := Mux(runtime_started && frontend.io.busy, busy_counter + 1.U, 0.U)
+  assert(busy_counter < 10000000.U, "BuckyballAccelerator: busy for too long!")
 }

arch/src/main/scala/framework/system/core/accelerator/RushB.scala

@@ -8,14 +8,14 @@ import framework.system.core.rocket.RoCCCommandBB
 /** Enables the Verilator-only rushB command source at elaboration time. */
 case object BuckyballRushBKey extends Field[Boolean](false)
 
-/** rushB ABI ID: tile ID in the high half, local accelerator index below it. */
-object RushBAcceleratorId {
+/** rushB ABI ID: tile ID in the high half, local Core index below it. */
+object RushBCoreId {
   private val LocalIdBits = 16
   private val LocalIdMask = (1 << LocalIdBits) - 1
 
   def apply(tileId: Int, localIndex: Int): Int = {
     require(tileId >= 0 && tileId < (1 << LocalIdBits), s"tile ID does not fit rushB ABI: $tileId")
-    require(localIndex >= 0 && localIndex <= LocalIdMask, s"accelerator index does not fit rushB ABI: $localIndex")
+    require(localIndex >= 0 && localIndex <= LocalIdMask, s"Core index does not fit rushB ABI: $localIndex")
     (tileId << LocalIdBits) | localIndex
   }
 
@@ -24,14 +24,14 @@ object RushBAcceleratorId {
 /**
  * Stable DPI boundary for host-driven RTL simulation.
  *
- * One instance is created for every Buckyball accelerator. The accelerator ID
- * is an ABI identifier, not a hart ID: heterogeneous systems may assign
- * arbitrary hart IDs and may give individual accelerators different configs.
+ * One instance is created for every RushB-capable Core. The Core ID is an ABI
+ * identifier, not a hart ID: heterogeneous systems may assign arbitrary hart
+ * IDs and may give individual Cores different configs.
  */
-class RushBCommandDPI(acceleratorId: Int, xLen: Int)
+class RushBCommandDPI(coreId: Int, xLen: Int)
     extends BlackBox(Map(
-      "ACCELERATOR_ID" -> acceleratorId,
-      "XLEN"           -> xLen
+      "CORE_ID" -> coreId,
+      "XLEN"    -> xLen
     ))
     with HasBlackBoxInline {
 
@@ -49,7 +49,7 @@ class RushBCommandDPI(acceleratorId: Int, xLen: Int)
     "RushBCommandDPI.v",
     """
       |module RushBCommandDPI #(
-      |  parameter integer ACCELERATOR_ID = 0,
+      |  parameter integer CORE_ID = 0,
       |  parameter integer XLEN = 64
       |)(
       |  input clock, input ready, input retired,
@@ -58,36 +58,36 @@ class RushBCommandDPI(acceleratorId: Int, xLen: Int)
       |  output logic [XLEN-1:0] rs1Data, output logic [XLEN-1:0] rs2Data
       |);
       |  import "DPI-C" function void verilator_rushb_peek(
-      |    input int accelerator_id,
+      |    input int core_id,
       |    output bit valid,
       |    output longint unsigned xs1_data,
       |    output longint unsigned xs2_data,
       |    output int unsigned funct);
-      |  import "DPI-C" function void verilator_rushb_accept(input int accelerator_id);
+      |  import "DPI-C" function void verilator_rushb_accept(input int core_id);
       |  import "DPI-C" function void verilator_rushb_observe(
-      |    input int accelerator_id, input bit valid, input bit ready);
+      |    input int core_id, input bit valid, input bit ready);
       |  import "DPI-C" function void verilator_rushb_report(
-      |    input int accelerator_id, input bit retired);
+      |    input int core_id, input bit retired);
       |
       |  bit accept_pending = 1'b0;
       |  int unsigned dpi_funct;
       |
       |  always @(posedge clock) begin
-      |    verilator_rushb_observe(ACCELERATOR_ID, valid, ready);
+      |    verilator_rushb_observe(CORE_ID, valid, ready);
       |    accept_pending <= valid && ready;
-      |    verilator_rushb_report(ACCELERATOR_ID, retired);
+      |    verilator_rushb_report(CORE_ID, retired);
       |  end
       |
       |  always @(negedge clock) begin
       |    if (accept_pending) begin
-      |      verilator_rushb_accept(ACCELERATOR_ID);
+      |      verilator_rushb_accept(CORE_ID);
       |      accept_pending <= 1'b0;
       |      valid = 1'b0;
       |    end else if (!valid) begin
       |      // DPI calls mutate C++ state without creating an RTL event. Load a
       |      // one-entry register on the falling edge, so command bits are
       |      // stable for the full following sampling edge.
-      |      verilator_rushb_peek(ACCELERATOR_ID, valid, rs1Data, rs2Data, dpi_funct);
+      |      verilator_rushb_peek(CORE_ID, valid, rs1Data, rs2Data, dpi_funct);
       |      funct = dpi_funct[6:0];
       |    end
       |  end
@@ -103,14 +103,14 @@ class RushBCommandDPI(acceleratorId: Int, xLen: Int)
   )
 }
 
-class RushBCommandBridge(acceleratorId: Int, xLen: Int) extends Module {
+class RushBCommandBridge(coreId: Int, xLen: Int) extends Module {
 
   val io = IO(new Bundle {
     val cmd     = Decoupled(new RoCCCommandBB(xLen))
     val retired = Input(Bool())
   })
 
-  val dpi = Module(new RushBCommandDPI(acceleratorId, xLen))
+  val dpi = Module(new RushBCommandDPI(coreId, xLen))
   dpi.io.clock   := clock
   dpi.io.ready   := io.cmd.ready
   dpi.io.retired := io.retired

arch/src/main/scala/framework/system/tile/BBTile.scala

@@ -42,12 +42,7 @@ import freechips.rocketchip.util.BooleanToAugmentedBoolean
 import framework.top.GlobalConfig
 import framework.system.core.rocket.RocketBB
 import framework.system.core.rocket.id.RVVRoCCDecode
-import framework.system.core.accelerator.{
-  BuckyballAccelerator,
-  BuckyballRushBKey,
-  RushBAcceleratorId,
-  RushBCommandBridge
-}
+import framework.system.core.accelerator.{BuckyballAccelerator, BuckyballRushBKey, RushBCommandBridge, RushBCoreId}
 import framework.memdomain.backend.MemRequestIO
 import framework.memdomain.backend.shared.SharedMemBackend
 import framework.memdomain.backend.shared.SharedMemLayout
@@ -637,7 +632,7 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC
       acc.map { accelerator =>
         if (rushBEnabled) {
           val source = Module(new RushBCommandBridge(
-            RushBAcceleratorId(outer.bbParams.tileId, i),
+            RushBCoreId(outer.bbParams.tileId, i),
             accelerator.b.core.xLen
           ))
           source.io.retired := accelerator.io.retired

arch/src/main/scala/sims/verilator/BBsimDRAM.scala

@@ -185,6 +185,11 @@ class BBSimDRAM(
       |  reg [1:0] __b_resp_reg;
       |
       |  always @(posedge clock) begin
+      |    if (!initialized) begin
+      |      channel = bbsim_memory_init(CHIP_ID, MEM_SIZE, WORD_SIZE, LINE_SIZE, ID_BITS, CLOCK_HZ, MEM_BASE);
+      |      initialized = 1'b1;
+      |    end
+      |
       |    if (reset) begin
       |      __ar_ready = 1'b0;
       |      __aw_ready = 1'b0;
@@ -198,11 +203,6 @@ class BBSimDRAM(
       |      __r_valid_reg  <= 1'b0;
       |      __b_valid_reg  <= 1'b0;
       |    end else begin
-      |      if (!initialized) begin
-      |        channel = bbsim_memory_init(CHIP_ID, MEM_SIZE, WORD_SIZE, LINE_SIZE, ID_BITS, CLOCK_HZ, MEM_BASE);
-      |        initialized = 1'b1;
-      |      end
-      |
       |      bbsim_memory_tick(
       |        channel,
       |

bb-tests/workloads/CMakeLists.txt

@@ -57,7 +57,7 @@ execute_process(
     --isa-dir "${BUCKYBALL_ISA_DIR}"
     --print-targets
     --print-target-balls
-    --print-core-targets
+    --print-rushb-targets
   RESULT_VARIABLE BUCKYBALL_TARGET_REGISTRY_RESULT
   OUTPUT_VARIABLE BUCKYBALL_TARGETS_RAW
   ERROR_VARIABLE BUCKYBALL_TARGET_REGISTRY_ERROR)
@@ -83,23 +83,49 @@ string(REPLACE "\n" ";" BUCKYBALL_BANK_TARGETS
   "${BUCKYBALL_BANK_TARGETS_RAW}")
 list(REMOVE_ITEM BUCKYBALL_BANK_TARGETS "")
 set(BUCKYBALL_TARGET_BALL_LINES)
-set(BUCKYBALL_CORE_TARGET_LINES)
+set(BUCKYBALL_RUSHB_TARGET_LINES)
 foreach(BUCKYBALL_TARGET_LINE ${BUCKYBALL_TARGETS})
   if(BUCKYBALL_TARGET_LINE MATCHES "^([0-9]+):([^,]+)$")
-    set(BUCKYBALL_CORE_TARGET_${CMAKE_MATCH_1} "${CMAKE_MATCH_2}")
-    list(APPEND BUCKYBALL_CORE_TARGET_LINES ${BUCKYBALL_TARGET_LINE})
+    list(APPEND BUCKYBALL_RUSHB_TARGET_LINES ${BUCKYBALL_TARGET_LINE})
   elseif(BUCKYBALL_TARGET_LINE MATCHES "^([^:]+):(.*)$")
     set(BUCKYBALL_TARGET_BALLS_${CMAKE_MATCH_1} "${CMAKE_MATCH_2}")
     list(APPEND BUCKYBALL_TARGET_BALL_LINES ${BUCKYBALL_TARGET_LINE})
   endif()
 endforeach()
 list(REMOVE_ITEM BUCKYBALL_TARGETS ${BUCKYBALL_TARGET_BALL_LINES}
-  ${BUCKYBALL_CORE_TARGET_LINES} "")
+  ${BUCKYBALL_RUSHB_TARGET_LINES} "")
 if(NOT BUCKYBALL_TARGETS)
   message(FATAL_ERROR "Chip.pb has no compiler targets")
 endif()
 message(STATUS "Buckyball compiler targets: ${BUCKYBALL_TARGETS}")
 message(STATUS "Buckyball bank targets: ${BUCKYBALL_BANK_TARGETS}")
+message(STATUS "Buckyball rushB targets: ${BUCKYBALL_RUSHB_TARGET_LINES}")
+
+function(buckyball_rushb_cores OUT_VAR TARGET)
+  set(_cores)
+  foreach(_entry IN LISTS BUCKYBALL_RUSHB_TARGET_LINES)
+    if(_entry MATCHES "^([0-9]+):(.+)$")
+      set(_core "${CMAKE_MATCH_1}")
+      set(_target "${CMAKE_MATCH_2}")
+      if(_target STREQUAL "${TARGET}")
+        list(APPEND _cores "${_core}")
+      endif()
+    endif()
+  endforeach()
+  set(${OUT_VAR} "${_cores}" PARENT_SCOPE)
+endfunction()
+
+function(buckyball_rushb_default_core OUT_VAR TARGET)
+  buckyball_rushb_cores(_cores "${TARGET}")
+  # Core ID 0 is valid, but CMake treats the string "0" as false.
+  # Test for an empty list explicitly so the first Core is accepted.
+  if("${_cores}" STREQUAL "")
+    message(FATAL_ERROR
+      "target '${TARGET}' has no RushB-capable Core in Chip.pb")
+  endif()
+  list(GET _cores 0 _core)
+  set(${OUT_VAR} "${_core}" PARENT_SCOPE)
+endfunction()
 
 function(buckyball_assign_physical_banks TARGET OUT)
   list(FIND BUCKYBALL_BANK_TARGETS "${TARGET}" _bank_target_index)
@@ -127,7 +153,7 @@ set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=rv64gc")
 set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -static -Wl,--no-dynamic-linker")
 
 function(add_buckyball_rushb_native TARGET_NAME)
-  cmake_parse_arguments(ARG "CXX" "OUTPUT_SUBDIR" "SOURCES;INCLUDE_DIRS;DEPENDS" ${ARGN})
+  cmake_parse_arguments(ARG "CXX" "OUTPUT_SUBDIR;CORE_ID" "SOURCES;INCLUDE_DIRS;DEPENDS" ${ARGN})
 
   if(NOT ARG_SOURCES)
     message(FATAL_ERROR "${TARGET_NAME}: rushB runner has no sources")
@@ -140,6 +166,13 @@ function(add_buckyball_rushb_native TARGET_NAME)
     message(FATAL_ERROR
       "add_buckyball_rushb_native requires BUILD_BIN_DIR and OUTPUT_BIN_DIR")
   endif()
+  if(NOT DEFINED ARG_CORE_ID OR ARG_CORE_ID STREQUAL "")
+    set(ARG_CORE_ID 0)
+  endif()
+  if(NOT ARG_CORE_ID MATCHES "^[0-9]+$")
+    message(FATAL_ERROR
+      "${TARGET_NAME}: RushB CORE_ID must be a non-negative integer")
+  endif()
 
   set(RUSHB_OUTPUT_ROOT ${OUTPUT_BIN_DIR}/${ARG_OUTPUT_SUBDIR})
   set(RUSHB_SYNC_ROOT ${BUILD_BIN_DIR}/${ARG_OUTPUT_SUBDIR})
@@ -171,7 +204,9 @@ function(add_buckyball_rushb_native TARGET_NAME)
       set(RUSHB_LIBRARY ${BUCKYBALL_RUSHB_BEMU_LIBRARY})
       set(RUSHB_LIBRARY_NAME bebop_bemu)
       set(RUSHB_BUILD_RUNTIME
-        COMMAND ${CMAKE_COMMAND} -E env CARGO_TARGET_DIR=${BUCKYBALL_CARGO_TARGET_DIR}
+        COMMAND ${CMAKE_COMMAND} -E env
+                --unset=CC --unset=CXX
+                CARGO_TARGET_DIR=${BUCKYBALL_CARGO_TARGET_DIR}
                 cargo build --release --manifest-path ${BUCKYBALL_RUSHB_BEMU_MANIFEST} --lib)
       set(RUSHB_RUNTIME_DEPENDENCY ${BUCKYBALL_RUSHB_BEMU_MANIFEST})
     else()
@@ -221,6 +256,7 @@ function(add_buckyball_rushb_native TARGET_NAME)
       OUTPUT ${RUSHB_BINARY} ${RUSHB_INSTALLED} ${RUSHB_SYNCED}
       COMMAND ${CMAKE_COMMAND} -E make_directory ${RUSHB_BUILD_DIR}
       COMMAND ${RUSHB_COMPILER} -no-pie ${RUSHB_STANDARD} -O2 -DBUCKYBALL_RUSHB
+              -DBUCKYBALL_RUSHB_CORE_ID=${ARG_CORE_ID}
               ${RUSHB_INCLUDE_ARGS}
               ${ARG_SOURCES} ${BUCKYBALL_REPO_ROOT}/compiler/lib/RushBRuntime.c
               -L${RUSHB_LIBRARY_DIR} -l${RUSHB_LIBRARY_NAME}
@@ -311,6 +347,7 @@ function(add_toy_mlir_rushb)
      NOT DEFINED BUCKYBALL_RUSHB_VERILATOR_LIBRARY)
     return()
   endif()
+  buckyball_rushb_default_core(RUSHB_CORE_ID "${ARG_TARGET}")
 
   set(MLIR_SRC ${CMAKE_CURRENT_SOURCE_DIR}/${ARG_NAME}.mlir)
   set(RUSHB_OBJ ${CMAKE_CURRENT_BINARY_DIR}/${ARG_NAME}-rushB.o)
@@ -332,7 +369,7 @@ function(add_toy_mlir_rushb)
       -convert-math-to-llvm
       -finalize-memref-to-llvm
       -convert-func-to-llvm
-      -lower-buckyball-intrinsics-to-rushb
+      "-lower-buckyball-intrinsics-to-rushb=core_id=${RUSHB_CORE_ID}"
       -reconcile-unrealized-casts |
     ${BUDDY_TRANSLATE} --buddy-to-llvmir |
     ${BUDDY_LLC} -filetype=obj -mtriple=x86_64 -O2 -o ${RUSHB_OBJ}
@@ -349,6 +386,7 @@ function(add_toy_mlir_rushb)
   add_buckyball_rushb_native(${ARG_TARGET_STEM}
     ${RUSHB_CXX_FLAG}
     OUTPUT_SUBDIR src/CTest/rushB
+    CORE_ID ${RUSHB_CORE_ID}
     SOURCES ${ARG_SOURCES} ${RUSHB_OBJ}
     INCLUDE_DIRS ${ARG_INCLUDE_DIRS}
     DEPENDS ${RUSHB_OBJ} ${ARG_DEPENDS})

bb-tests/workloads/lib/bbhw/isa/00_fence.c

@@ -5,13 +5,19 @@
 
 #define BB_FENCE_FUNC7 0
 
+#if defined(BUCKYBALL_RUSHB)
+#define bb_dma_cache_flush()                                                   \
+  do {                                                                         \
+  } while (0)
+#define bb_fence() BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_FENCE_FUNC7)
+#else
 #define bb_dma_cache_flush() asm volatile("fence.i" ::: "memory")
-
 #define bb_fence()                                                             \
   do {                                                                         \
     BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_FENCE_FUNC7);                           \
     asm volatile("fence rw, rw" ::: "memory");                                 \
     bb_dma_cache_flush();                                                      \
   } while (0)
+#endif
 
 #endif // _BB_FENCE_H_

bb-tests/workloads/lib/bbhw/isa/16_mvout.c

@@ -26,6 +26,7 @@
     BB_MVOUT_TOUCH(_bb_mo_addr, _bb_mo_depth, _bb_mo_stride, _bb_mo_bank);     \
     bb_dma_cache_flush();                                                      \
     rushb_mvout(                                                               \
+        BUCKYBALL_RUSHB_CORE,                                                  \
         (uint64_t)(BB_BANK0(_bb_mo_bank) | BB_ITER(_bb_mo_depth)),             \
         (uint64_t)(FIELD(_bb_mo_addr, 0, 38) | FIELD(_bb_mo_stride, 39, 57)),  \
         (void *)_bb_mo_addr);                                                  \

bb-tests/workloads/lib/bbhw/isa/32_mset.c

@@ -14,10 +14,11 @@
 
 #if defined(BUCKYBALL_RUSHB)
 #define bb_mset(bank_id, alloc, row, col)                                      \
-  rushb_mset((uint64_t)BB_BANK0(bank_id),                                      \
+  rushb_mset(BUCKYBALL_RUSHB_CORE, (uint64_t)BB_BANK0(bank_id),                \
              (uint64_t)BB_MSET_RS2(row, col, alloc, 0))
 #define bb_mset_clear(bank_id, row, col)                                       \
-  rushb_mset((uint64_t)BB_BANK0(bank_id), (uint64_t)BB_MSET_RS2(row, col, 1, 1))
+  rushb_mset(BUCKYBALL_RUSHB_CORE, (uint64_t)BB_BANK0(bank_id),                \
+             (uint64_t)BB_MSET_RS2(row, col, 1, 1))
 #else
 #define bb_mset(bank_id, alloc, row, col)                                      \
   BUCKYBALL_INSTRUCTION_R_R(BB_BANK0(bank_id),                                 \