This repository features a curated reading list of papers on AI for Chips/Very Large Scale Integration (VLSI)/Electronic Design Automation (EDA). The papers are primarily categorized by chip design task type.We're continuously improving this repository. In addition to papers accepted by top-tier conferences and journals, we also include the latest research from arXiv. If you find any relevant papers that should be added, please feel free to submit a pull request (PR) or open an issue. If you find this repository helpful, please consider giving it a 🌟!
This repository is built upon the survey "A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA" published by Professor Xie Zhiyao's research group.
| Date | Method | Type | Conference | Paper Title and Paper Interpretation (In Chinese) | Code |
|---|---|---|---|---|---|
| 2023-01-16 | GNN-IC-Reliability-Security |  |
ASP-DAC 2023 (pp. 83-90) | Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs | |
| 2023-09-14 | EDA-GNN-Survey | |
ACM TODAES (Trans. on Design Automation of Electronic Systems), Vol. 26, No. 6, 2022/2023 | A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications | |
| 2023-10 | LLM4SS | |
Access | LLM for SoC Security: A Paradigm Shift | |
| 2023-12-28 | Llm4eda | |
arXiv | Llm4eda: Emerging progress in large language models for electronic design automation | paper list |
| 2024-03 | LCM | |
SCIS 2024 | Large circuit models: opportunities and challenges. | |
| 2024-03-12 | FutureOrMirage | |
ISPD 2024 (pp. 65-66); extended journal version ACM TODAES 30(6), 2025 | Large Language Models for EDA: Future or Mirage? | |
| 2024-05 | LFCD | |
ISVLSI 2024 | Llms and the future of chip design: Unveiling security risks and building trust | |
| 2024-06 | llm-guided | |
GLSVLSI 2024 | Navigating soc security landscape on llm-guided paths | |
| 2024-10-24 | Llm-aided | |
arXiv | Llm-aided efficient hardware design automation | |
| 2024-12 | HdvLlm | |
Electronics 2025 | Hardware design and verification with large language models: A scoping review, challenges, and open issues | |
| 2025-01 | LLM4EDA | |
TODAES 2025 | A survey of research in large language models for electronic design automation | |
| 2025-01-20 | SimEval | |
ASP-DAC 2025 (pp. 1002-1007) | SimEval: Investigating the Similarity Obstacle in LLM-based Hardware Code Generation | |
| 2025-03 | 🌟FoundationAI | |
arXiv | A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA | |
| 2025-06-17 | CVDP | |
arXiv | Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification | CVDP |
| 2025-06-22 | LLMsDrivingForce | |
DAC 2025 (62nd ACM/IEEE DAC) | LLMs: A Driving Force in Next Generation Digital Design Automation | |
| 2025-07-20 | MMCircuitEval | |
ICCAD 2025 | MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs | MMCircuitEval |
| 2025-07-22 | RealBench | |
arXiv | RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs | RealBench |
| 2025-08 | LLMsEDA | |
arXiv | Large Language Models (LLMs) for Electronic Design Automation (EDA) | |
| 2025-09-05 | RevolutionOrHype | |
ICCAD 2025 (invited panel paper) | Revolution or Hype? Seeking the Limits of Large Models in Hardware Design | |
| 2026-01-05 | RTL-OPT | |
arXiv | A New Benchmark for the Appropriate Evaluation of RTL Code Optimization | |
| 2026-01-29 | ChipBench | |
arXiv | ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design | ChipBench |
| 2026-04-16 | HWE-Bench | |
arXiv | HWE-Bench: Benchmarking LLM Agents on Real-World Hardware Bug Repair Tasks | |
| 2026-04-26 | LLMsFailRTL | |
arXiv (under submission for EMNLP 2026) | How LLMs Fail and Generalize in RTL Coding for Hardware Design? | |
| 2026-05-15 | RTL-BenchMT | |
DAC 2026 | RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision | |
| 2026-05-26 | AssertLLM2 | |
arXiv | AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications | |
| 2026-06-08 | RTL-BenchLS | |
arXiv | RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models |
| Date | Method | Conference | Paper Title and Paper Interpretation (In Chinese) | Code |
|---|---|---|---|---|
| 2023-10-28 | HARP | ICCAD 2023 | Robust GNN-based Representation Learning for HLS | |
| 2024-5-25 | Synthai | arXiv | Synthai: A multi agent generative ai framework for automated modular hls design generation. | |
| 2024-6-13 | ProgSG | MLCAD 2024 | Cross-modality program representation learning for electronic design automation with high-level synthesis. | |
| 2024-08-13 | Hlspilot | ICCAD 2024 | Hlspilot: Llm-based high-level synthesis | |
| 2024-8-19 | LLMs4HLS | ICCAD 2024 | Are llms any good for high-level synthesis? | |
| 2024-11-29 | C2hlsc | TODAES 2024 | C2hlsc: Leveraging large language models to bridge the software-tohardware design gap | |
| 2025-2-19 | LLM-assisted-HLS | ASP-DAC 2025 | Exploring code language models for automated hls-based hardware generation: Benchmark, infrastructure and analysis | |
| 2025-04-20 | HLSTester | ICCAD 2025 | HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis | |
| 2025-7-1 | ChatHLS | arXiv | ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis | |
| 2025-07-29 | HLSDebugger | ICCAD 2025 | HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions | HLSDebugger |
| 2026-02-01 | Pragmas2Partners | LATTE 2026 | From Pragmas to Partners: A Symbiotic Evolution of Agentic High-Level Synthesis | |
| 2026-04-10 | DiffHLS | arXiv | DiffHLS: Differential Learning for High-Level Synthesis QoR Prediction with GNNs and LLM Code Embeddings |
| Date | Method | Type | Conference | Paper Title and Paper Interpretation (In Chinese) | Code |
|---|---|---|---|---|---|
| 2020-8-27 | Dave | MLCAD 2020 | Dave: Deriving automatically verilog from english | ||
| 2021-10-10 | Design2Vec | NeurIPS 2021 | Learning semantic representations to verify hardware designs | ||
| 2022-12-13 | VGen🔥 | DATE 2023 | Benchmarking large language models for automated verilog rtl code generation | VGen | |
| 2023-2-17 | Generating secure hardware using chatgpt resistant to cwes | ||||
| 2023-5-22 | Chip-chat🔥 | MLCAD 2023 | Chip-chat: Challenges and opportunities in conversational hardware design | ChipChatData | |
| 2023-5-23 | Chipgpt🔥 | arXiv | Chipgpt: How far are we from natural language hardware design | ||
| 2023-7-28 | VeriGen🔥 | TODAES 2024 | Verigen: A large language model for verilog code generation | VeriGen | |
| 2023-9-14 | Verilogeval🔥 | ICCAD 2023 | Verilogeval: Evaluating large language models for verilog code generation | verilog-eval | |
| 2023-9-19 | GPT4AIGChip🔥 | ICCAD 2023 | GPT4AIGChip: Towards next-generation AI accelerator design automation via large language models. | ||
| 2023-10-31 | ChipNeMo🔥 | arXiv | ChipNeMo: Domain-Adapted LLMs for Chip Design | ||
| 2023-11-8 | Autochip🔥 | arXiv | Autochip: Automating hdl generation using llm feedback | AutoChip | |
| 2023-12-8 | SNS v2 | MICRO 2023 | Fast, robust and transferable prediction for hardware logic synthesis | ||
| 2023-12-14 | Rtlcoder | TCAD 2024 | Rtlcoder: Fully open-source and efficient llm-assisted rtl code generation technique | RTL-Coder | |
| 2024-01-01 | MasterRTL | IEEE TCAD (DOI 10.1109/TCAD.2024.3420904) | Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques | ||
| 2024-1-12 | AttenSink | arxiv | Zero-shot rtl code generation with attention sink augmented large language models | ||
| 2024-2-5 | MCTS | arxiv | Make every move count: Llm-based high-quality rtl code generation using mcts | ||
| 2024-2-23 | Betterv | ICML 2024 | Betterv: Controlled verilog generation with discriminative guidance | ||
| 2024-3-11 | En2asic | arxiv | From english to asic: Hardware implementation with large language model | ||
| 2024-3-17 | chipgptft | DAC 2024 | Data is all you need: Finetuning llms for chip design via an automated design-data augmentation framework | chipgptft | |
| 2024-4-12 | Creativeval | LAD 2024 | Creativeval: Evaluating creativity of llm-based hardware code generation | CreativEval | |
| 2024-5-27 | Rtl-repo | LAD 2024 | Rtl-repo: A benchmark for evaluating llms on large-scale rtl design projects | code | |
| 2024-6-6 | Vhdl-eval | LAD 2024 | Vhdl-eval: A framework for evaluating large language models in vhdl code generation | ||
| 2024-7-2 | Mg-verilog | LAD 2024 | Mg-verilog: Multi-grained dataset towards enhanced llm-assisted verilog generation | code | |
| 2024-7-4 | CBA | arxiv | Classification-based automatic hdl code generation using llms | ||
| 2024-7-11 | chipgptv | ICCAD 2024 | Natural language is not enough: Benchmarking multi-modal generative ai for verilog generation | code | |
| 2024-7-15 | Codev | arxiv | Codev: Empowering llms for verilog generation through multi-level summarization | CodeV | |
| 2024-7-21 | VeriSeek | arxiv | Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning | ||
| 2024-7-23 | Origen | ICCAD 2024 | Origen: Enhancing rtl code generation with code-to-code augmentation and self-reflection | OriGen | |
| 2024-7-23 | Hp4lcd | MLCAD 2024 | Rome was not built in a single step: Hierarchical prompting for llm-based chip design | ||
| 2024-7-24 | Autovcoder | ICCD 2024 | Autovcoder: A systematic framework for automated verilog code generation using llms | AutoVCoder | |
| 2024-8-15 | Verilogcoder | AAAI 2025 | Verilogcoder: Autonomous verilog coding agents with graph-based planning and abstract syntax tree (ast)-based waveform tracing tool | VerilogCoder | |
| 2024-8-20 | ReVerilogeval | arxiv | Revisiting verilogeval: Newer llms, in-context learning, and specification-to-rtl tasks | ||
| 2024-09-04 | RTLRewriter | ICCAD 2024 | RTLRewriter: Methodologies for Large Models aided RTL Code Optimization | ||
| 2024-9-9 | CoDes | MLCAD 2024 | Chain-of-descriptions: Improving code llms for vhdl code generation and summarization | ||
| 2024-9-19 | Craftrtl | ICLR 2025 | Craftrtl: High-quality synthetic data generation for verilog code models with correct-by-construction non-textual representations and targeted code repair | craftrtl | |
| 2024-11-5 | MetRex | ASP- DAC 2025 | MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs | MetRex | |
| 2024-11-21 | AIVRIL2 | DATE 2025 | Eda-aware rtl generation with large language models | ||
| 2024-11-25 | Opl4gpt | ASP-DAC 2025 | Opl4gpt: An application space exploration of optimal programming language for hardware design by llm | ||
| 2024-12-09 | PyraNet | DAC 2025 | PyraNet: A Multi-Layered Hierarchical Dataset for Verilog | PyraNet | |
| 2024-12-10 | Mage | DAC 2025 | Mage: A multi-agent engine for automated rtl code generation | MAGE | |
| 2025-1-6 | Rtlsquad | arxiv | Rtlsquad: Multi-agent based interpretable rtl design | ||
| 2025-01-09 | HaVen | DATE 2025 | HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers | ||
| 2025-01-20 | LLSM | ASP-DAC 2025 (30th Asia and South Pacific Design Automation Conference; DOI 10.1145/3658617.3697618) | LLSM: LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting, Hybrid Embedding and AIG-tailored Acceleration | ||
| 2025-2-15 | Lintllm | arxiv | Lintllm: An open-source verilog linting framework based on large language models | ||
| 2025-2-20 | Deeprtl | ICLR 2025 | Deeprtl: Bridging verilog understanding and generation with a unified representation model | ||
| 2025-3-4 | CircuitEncoder | ASP-DAC 2025 | A self-supervised, pre-trained, and cross-stage-aligned circuit encoder provides a foundation for various design tasks | ||
| 2025-03-18 | VFlow | arxiv | VFlow: Discovering Optimal Agentic Workflows for Verilog Generation | ||
| 2025-3-19 | Openllm-rtl | ICCAD 2024 | Openllm-rtl: Open dataset and benchmark for llm-aided design rtl generation | ||
| 2025-03-27 | RocketPPA | arxiv | RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Experts | ||
| 2025-03-30 | HDLCORE | arxiv | HDLCORE: A TRAINING-FREE FRAMEWORK FOR MIT-IGATING HALLUCINATIONS IN LLM-GENERATED HDL | ||
| 2025-04-20 | ReasoningV | arXiv | ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model | ReasoningV | |
| 2025-5-4 | Circuitfusion | ICLR 2025 | Circuitfusion: multimodal circuit representation learning for agile chip design | CircuitFusion | |
| 2025-5-9 | Spec2Doc2RTL | ISEDA | Spec2Doc2RTL: RTL Generation from Specification with Natural Language Representation | ||
| 2025-05-09 | FreeV | DAC 2025 | Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs | ||
| 2025-5-21 | LLM4GV | DATE 2025 | LLM4GV: An LLM-Based Flexible Performance-Aware Framework for GEMM Verilog Generation | ||
| 2025-5-21 | Data Augmentation and RL | DATE 2025 | Improving LLM-Based Verilog Code Generation with Data Augmentation and RL | ||
| 2025-5-21 | VToT | DATE 2025 | VToT: Automatic Verilog Generation via LLMs with Tree of Thoughts Prompting | ||
| 2025-05-30 | CodeV-R1 | NeurIPS 2025 | QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation | CodeV-R1 | |
| 2025-06-01 | MOSS | DAC 2025 (62nd ACM/IEEE Design Automation Conference) | MOSS: Multi-Modal Representation Learning on Sequential Circuits | ||
| 2025-06-24 | PPA-RTL | DAC 2025 | Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMs | ||
| 2025-6-26 | OpenRTLSet | ICLAD 2025 | OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design | ||
| 2025-6-26 | EvoVerilog | arxiv | EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code | ||
| 2025-07-07 | ChipSeek-R1 | ACL 2026 | ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning | ||
| 2025-07-20 | VeriOpt | ICCAD 2025 | VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs | ||
| 2025-08-25 | VeriRL | arXiv | VeriRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning | VeriRL | |
| 2025-08-26 | SynCircuit | DAC 2025 | SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits | ||
| 2025-09-01 | SynC-LLM | EMNLP 2025 | SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models | SynC-LLM | |
| 2025-10-26 | FADR | ICCAD 2025 | Building Reasoning LLMs for Hardware Design Generation via Function-Aligned Differentiated Revision | ||
| 2025-10-26 | LLM4Verilog | ICCAD 2025 | LLM4Verilog: Building Large-Scale, High-Quality Data Infrastructure for Verilog Code Generation via Community Efforts | ||
| 2025-11-08 | ArchCraft | arXiv | Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework | ||
| 2025-11-15 | EARL | CTS 2026 (Chips to Systems Conference) | EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation | ||
| 2025-11-20 | CorrectHDL | arXiv | CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference | ||
| 2025-11-25 | QiMeng-CRUX | AAAI 2026 | QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Design | QiMeng-CRUX | |
| 2025-11-25 | Invertible-HDL | arXiv | Mitigating hallucinations and omissions in LLMs for invertible problems: An application to hardware logic design automation | ||
| 2025-11-27 | VeriDispatcher | arXiv | VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimization | ||
| 2025-12-04 | David vs. Goliath | arXiv | David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design? | ||
| 2025-12-05 | ChipMind | AAAI 2026 | ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications | ||
| 2026-01-26 | EvolVE | arXiv | EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization | EvolVE | |
| 2026-01-31 | LocalV | arXiv | LocalV: Exploiting Information Locality for IP-level Verilog Generation | ||
| 2026-02-03 | LLM-FSM | arXiv | LLM-FSM: Scaling Large Language Models for Finite-State Reasoning in RTL Code Generation | ||
| 2026-02-10 | ACE-RTL | arXiv | ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs | ||
| 2026-02-10 | SiliconMind-V1 | arXiv | SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation | ||
| 2026-03-29 | RTLSeek | DAC 2026 | RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning | RTLSeek | |
| 2026-04-16 | VeriGraphi | arXiv | VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs | ||
| 2026-04-16 | Dr. RTL | ICCAD 2026 | Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement | ||
| 2026-04-16 | Self-Evolved ABC | DAC 2026 | Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC | ||
| 2026-04-20 | VerilogCL | arXiv | VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation | ||
| 2026-04-21 | ChipCraftBrain | arXiv | ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration | ||
| 2026-04-25 | LEGO | ISEDA 2026 | LEGO: An LLM Skill-Based Front-End Design Generation Platform | ||
| 2026-05-03 | PipeRTL | arXiv | PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation | ||
| 2026-05-13 | ChipMATE | arXiv | ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation | ChipMATE | |
| 2026-05-20 | Trace2Skill | arXiv | Trace2Skill: Verifier-Guided Skill Evolution for Long-Context EDA Agents | ||
| 2026-05-26 | Verilog-Evolve | arXiv | Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation | ||
| 2026-06-02 | StepPRM-RTL | DAC 2026 | StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis | ||
| 2026-06-03 | Alpha-RTL (TTT-RTL) | arXiv | Alpha-RTL: Test-Time Training for RTL Hardware Optimization | ||
| 2026-06-06 | ROSUM-MCTS | arXiv | ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards | ||
| 2026-07-17 | RTL-Sequencer | DAC 2026 | RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm |
| Date | Method | Conference | Paper Title and Paper Interpretation (In Chinese) | Code |
|---|---|---|---|---|
| 2023-06-03 | NL2SVA | DAV 2023 | Towards improving verification productivity with circuitaware translation of natural language to systemverilog assertions | |
| 2023-09-18 | AutoSVA2 | arxiv | Using LLMs to facilitate formal verification of RTL | |
| 2023-10-06 | LLM4DV | FCCM 2025 | Llm4dv: Using large language models for hardware test stimuli generation. | ml4dv |
| 2023-11-28 | RTLFixer🔥 | DAC 2024 | Rtlfixer: Automatically fixing rtl syntax errors with large language models | RTLFixer |
| 2024-01-31 | ChIRAAG | ISVLSI 2024 | Chiraag: Chatgpt informed rapid and automated assertion generation. | ChIRAAG |
| 2024-02-01 | AssertLLM | ASP-DAC 2025 | AssertLLM: Generating and evaluating hardware verification assertions from design specifications via multi-LLMs. | AssertLLM |
| 2024-03-18 | HDLDebugger | TODAES 2024 | Hdldebugger: Streamlining hdl debugging with large language models | |
| 2024-05-10 | MEIC | ICCAD 2024 | Meic: Re-thinking rtl debug automation using llms | |
| 2024-05-29 | VTS 2024 | Domain-adapted llms for vlsi design and verification: A case study on formal verification | ||
| 2024-05-31 | VeriAssist | arxiv | Towards llm-powered verilog rtl assistant: Self-verification and self-correction | |
| 2024-06-03 | VerilogReader | LAD 2024 | Verilogreader: Llm-aided hardware test generation | |
| 2024-06-10 | DATE 2024 | Llm-based processor verification: A case study for neuronnorphic processor. | ||
| 2024-06-24 | Latg | arxiv | Llm-aided testbench generation and bug detection for finite-state machines. | |
| 2024-06-26 | AssertionBench | arxiv | Assertionbench: A benchmark to evaluate large-language models for assertion generation | |
| 2024-8-15 | Verilogcoder | AAAI 2025 | Verilogcoder: Autonomous verilog coding agents with graph-based planning and abstract syntax tree (ast)-based waveform tracing tool | VerilogCoder |
| 2024-09-23 | LiK | DAC 2025 | Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog | |
| 2024-10-01 | llmrag | LAD 2025 | From bugs to fixes: Hdl bug identification and patching using llms and rag | |
| 2024-10-15 | FVEval | DATE 2025 | Fveval: Understanding language model capabilities in formal verification of digital hardware | FVEval |
| 2024-11-13 | CorrectBench | DATE 2025 | CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design | CorrectBench |
| 2024-11-25 | UVLLM | arxiv | Uvllm: An automated universal rtl verification framework using llms. | |
| 2025-03-06 | AssertSolver | DAC 2025 | Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design | AssertSolver |
| 2025-03-31 | SSF | DATE 2025 | Early Functional Safety and PPA Evaluation of Digital Designs | |
| 2025-04-28 | UVM^2 | ICCAD 2025 | From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification | |
| 2025-06-13 | PRO-V | PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification | ||
| 2025-08-22 | ARSP | arXiv | ARSP: Automated Repair of Verilog Designs via Semantic Partitioning | |
| 2025-11-19 | CD-DPO (TB or not TB) | arXiv | TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generation | |
| 2026-03-03 | SpecLoop | arXiv | SpecLoop: An Agentic RTL-to-Specification Framework with Formal Verification Feedback Loop | |
| 2026-03-15 | CodeV-SVA | DAC 2026 | QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis | CodeV-SVA |
| 2026-04-10 | AgileAssert | arXiv | From Indiscriminate to Targeted: Functionally Critical Signal-Driven Assertion Generation using LLMs for Efficient RTL Verification | |
| 2026-05-06 | UVMarvel | DAC 2026 | UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification | |
| 2026-05-08 | CktFormalizer | arXiv | CktFormalizer: Autoformalization of Natural Language into Circuit Representations | |
| 2026-06-11 | STG | arXiv | Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation | |
| 2026-06-22 | VeriPilot | arXiv | VeriPilot: An LLM-Powered Verilog Debugging Framework | VeriPilot |
| 2026-07-28 | GoGoTB | ICCAD 2026 | GoGoTB: Agentic RTL Verification with Specification-Grounded Coverage Closure | |
| 2026-08-03 | VeriTrace | ICLAD 2026 | VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space | |
| 2026-08-10 | CHORUS | arXiv | CHORUS: Complementary Experts for High-Coverage Testbench Stimulus Generation |
| Date | Method | Conference | Paper Title and Paper Interpretation (In Chinese) | Code |
|---|---|---|---|---|
| 2021-12-03 | EZSVR🔥 | SP 2023 | Examining zero-shot vulnerability repair with large language models | |
| 2023-02 | TIFS 2024 | On hardware security bug code fixes by prompting large language models | ||
| 2023-06-24 | SAbyLLM | TIFS 2024 | (security) assertions by large language models | |
| 2023-08-14 | DIVAS | arxiv | Divas: An llm-based end-to-end framework for soc security analysis and policy-based protection | |
| 2023-08-21 | NSPG | arxiv | Unlocking hardware security assurance: The potential of llms | |
| 2023-10-10 | SCAR | TVLSI 2024 | Scar: Power side-channel analysis at rtl level | |
| 2023-11-26 | Netlist Whisperer | ASHES 2023 | Netlist whisperer: Ai and nlp fight circuit leakage! | |
| 2024-05 | SecRT-LLM | HOST 2024 | Empowering hardware security with llm: The development of a vulnerable hardware database | |
| 2024-05 | Self-HWDebug | ISVLSI 2024 | Self-hwdebug: Automation of llm self-instructing for hardware security verification | |
| 2024-10-01 | llmrag | LAD 2025 | From bugs to fixes: Hdl bug identification and patching using llms and rag | |
| 2024-11-26 | RTL-Breaker | DATE 2025 | RTL-Breaker: Assessing the Security of LLMs Against Backdoor Attacks on HDL Code Generation | |
| 2025-01-05 | RTLMarker | ASP-DAC 2025 | RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework | |
| |
| Date | Method | Conference | Paper Title and Paper Interpretation (In Chinese) | Code |
|---|---|---|---|---|
| 2023-06-12 | LCDA | arxiv | On the viability of using LLMs for SW/HW co-design: An example in designing CiM DNN accelerators. | |
| 2023-06-21 | BSD (AlphaChip / Enlightenment) | National Science Review (NSR) | Pushing the Limits of Machine Design: Automated CPU Design with AI | |
| 2023-07-17 | QGAS | arxiv | Unleashing the potential of LLMs for quantum computing: A study in quantum architecture design | |
| 2023-9-19 | GPT4AIGChip🔥 | ICCAD 2023 | GPT4AIGChip: Towards next-generation AI accelerator design automation via large language models. | |
| 2024-1-24 | SpecLLM | arxiv | SpecLLM: Exploring generation and review of vlsi design specification with large language model. | |
| 2024-06-23 | ChatCPU | DAC 2024 | ChatCPU: An Agile CPU Design & Verification Platform with LLM | |
| 2024-08-03 | BSD (Enlightenment-1 / QiMeng-CPU-v1) | IJCAI 2024 | Automated CPU Design by Learning from Input-Output Examples | |
| 2025-05-06 | State-BSD | IJCAI 2025 | QiMeng-CPU-v2: Automated Superscalar Processor Design by Learning Data Dependencies | |
| 2025-06-03 | LPCM | arXiv | Large Processor Chip Model | |
| 2025-08-08 | MAHL | ICCAD 2025 | MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging | |
| 2025-10-26 | MultiModel-DSE | ICCAD 2025 | LLM-Augmented Multi-Modal Fusion for SoC Design Space Exploration | |
| 2026-02-06 | Design Conductor (DC) | arXiv | Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU | |
| 2026-07-08 | ThermoDSE | arXiv | ThermoDSE: A Thermal-Aware and Comprehensive Design Space Exploration for Chiplet-Based DNN Accelerators | |
| 2026-08-10 | FSGen | DAC 2026 | FSGen: Agile Fused and Sparse Accelerator Generator with Accurate Power Model for LLM Applications | FSGen |
| 2026-08-26 | Redwood | arXiv | Redwood: A Frontier AI Accelerator Designed, Verified, and Deployed from Scratch in 2 Weeks by AI |
| Date | Method | Conference | Paper Title and Paper Interpretation (In Chinese) | Code |
|---|---|---|---|---|
| 2021-11-26 | DeepGate | DAC 2022 | DeepGate: Learning neural representations of logic gates | |
| 2022-8-23 | Fgnn | DAC 2022 | Functionality matters in netlist representation learning | |
| 2022-09-07 | TAG | ICCAD 2022 | TAG: Learning Circuit Spatial Embedding From Layouts | |
| 2022-11-07 | WhyGNN | ICCAD 2022 | Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper) | |
| 2023-02-27 | Deepseq | DATE | Deepseq: Deep sequential circuit learning. In Design, Automation and Test in Europe Conference and Exhibition | |
| 2023-03-14 | Gamora | DAC 2023 | Gamora: Graph learning based symbolic reasoning for large-scale boolean networks | |
| 2023-05-25 | DeepGate2 | ICCAD 2023 | DeepGate2: Functionality-aware circuit representation learning | |
| 2024-03-02 | Less is more | DAC 2024 | Less is more: Hop-wise graph attention for scalable and generalizable learning on circuits | |
| 2024-11-01 | Deepseq2 | ASP-DAC 2025 | Deepseq2: Enhanced sequential circuit learning with disentangled representations | |
| 2025-01-01 | Fgnn2 | TCAD 2024 | Fgnn2: A powerful pre-training framework for learning the logic functionality of circuits | |
| 2025-01-23 | Deepgate4 | ICLR 2025 | Deepgate4: Efficient and effective representation learning for circuit design at scale | |
| 2025-2-5 | Deepcell | arxiv | Deepcell: Multiview representation learning for post-mapping netlists | |
| 2025-2-18 | MGVGA | ICLR 2025 | Circuit representation learning with masked gatemodeling and verilog-aigalignment | |
| 2025-02-18 | CircuitAR | arXiv | Architect of the Bits World: Masked Autoregressive Modeling for Circuit Generation Guided by Truth Table | |
| 2025-3-4 | CircuitEncoder | ASP-DAC 2025 | A self-supervised, pre-trained, and cross-stage-aligned circuit encoder provides a foundation for various design tasks | |
| 2025-04-09 | Polargate | ICCAD 2024 | Polargate: Breaking the functionality representation bottleneck of and-inverter graph neural network | |
| 2025-04-12 | NetTAG | DAC 2025 | Nettag: A multimodal rtl-and-layoutaligned netlist foundation model via text-attributed graph | |
| 2025-04-13 | GenEDA | arxiv | GenEDA: Unleashing Generative Reasoning on Netlist via Multimodal Encoder-Decoder Aligned Foundation Model | |
| 2025-11-12 | DR-GNN | AAAI 2026 | DynamicRTL: RTL Representation Learning for Dynamic Circuit Behavior | DR-GNN |
| 2026-03-10 | WrongCode | arXiv | Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL | |
| 2026-08-28 | DeepSeq3 | arXiv | Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits | DeepSeq3 |
| Date | Method | Conference | Paper Title and Paper Interpretation (In Chinese) | Code |
|---|---|---|---|---|
| 2023-08 | ChatEDA | MLCAD 2023 | Chateda: A large language model powered autonomous agent for eda | ChatEDAv1 |
| 2024-05-24 | LLM4Scldof | LAD 2024 | Large language model (llm) for standard cell layout design optimization | |
| 2024-06-23 | LLM-HD | DAC 2024 | LLM-HD: Layout Language Model for Hotspot Detection with GDS Semantic Encoding | |
| 2024-07 | RAG-EDA | ICCAD 2024 | Customized retrieval augmented generation and benchmarking for eda tool documentation qa | RAG-EDA |
| 2024-07-15 | FabGPT | ICCAD 2024 | Fabgpt: An efficient large multimodal model for complex wafer defect knowledge queries | |
| 2024-08-24 | two-stage | AAAI 2024 | Intelligent opc engineer assistant for semiconductor manufacturing | |
| 2024-11-28 | DRC-Coder | arxiv | Drc-coder: Automated drc checker code generation using llm autonomous agent | |
| 2024-12 | ChipAlign | arxiv | Chipalign: Instruction alignment in large language models for chip design via geodesic interpolation | |
| 2025-02-15 | EDAid | NAACL 2025 | Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automation | |
| 2025-07-02 | CROP | ICCAD 2025 | CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs | |
| 2025-10-01 | OptAware-PRTP | IEEE TCAD 2025 | An Optimization-Aware Prerouting Timing Prediction Framework Based on Multimodal Learning | |
| 2025-10-18 | EDA-Copilot | ACM TODAES 2025 | EDA-Copilot: A RAG-Powered Intelligent Assistant for EDA Tools | |
| 2025-10-27 | MM-GRADE | ICCAD 2025 | MM-GRADE: A Multi-Modal EDA Tool Documentation QA Framework Leveraging Retrieval Augmented Generation | MM-GRADE |
| 2026-04-28 | EIM | DAC 2026 | How Can Reinforcement Learning Achieve Expert-level Placement? |
| Date | Method | Conference | Paper Title and Paper Interpretation (In Chinese) | Code |
|---|---|---|---|---|
| 2023-12 | LADAC | Ladac: Large language model-driven auto-designer for analog circuits | ||
| 2024-04-09 | ADO-LLM | ISCAS 2024 | Ado-llm: Analog design bayesian optimization with in-context learning of large language models | |
| 2024-05 | AnalogCoder | AAAI 2025 | Analogcoder: Analog circuit design via training-free code generation | AnalogCoder |
| 2024-05 | FLAG | ISCAS 2024 | Flag: Formula-llm-based auto-generator for baseband hardware | |
| 2024-07 | LaMAGIC | Lamagic: Language-model-based topology generation for analog integrated circuits | ||
| 2024-11 | Artisan | DAC 2024 | Artisan: Automated operational amplifier design via domain-specific large language model | |
| 2024-11-19 | LEDRO | Ledro: Llm-enhanced design space reduction and optimization for analog circuits | ||
| 2024-12-17 | AnalogXpert | Analogxpert: Automating analog topology synthesis by incorporating circuit design expertise into large language models | ||
| 2025-01-14 | LayoutCopilot | TCAD 2025 | LayoutCopilot: An LLM-Powered Multiagent Collaborative Framework for Interactive Analog Layout Design. | |
| 2025-02-28 | AnalogGenie | ICLR 2025 | Analoggenie: A generative engine for automatic discovery of analog circuit topologies | AnalogGenie |