From 4e0587fc74eed6903e32c1fdf655d5bcde1e1b15 Mon Sep 17 00:00:00 2001 From: mrehman Date: Tue, 8 Sep 2026 16:29:52 +0530 Subject: [PATCH 1/4] drivers: qcom: prng: add support for Nord and Shikra Add support for the Qualcomm CSRNG driver on Nord and Shikra platforms. Introduce the required platform-specific handling to enable CSRNG access from OP-TEE. Validation: - Build verified on Nord - Build verified on Shikra - CSRNG functionality validated on both platforms Signed-off-by: mrehman --- core/drivers/qcom/rng/qcom-csrng.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/core/drivers/qcom/rng/qcom-csrng.c b/core/drivers/qcom/rng/qcom-csrng.c index 1b7c6a15b..b9646c1fd 100644 --- a/core/drivers/qcom/rng/qcom-csrng.c +++ b/core/drivers/qcom/rng/qcom-csrng.c @@ -9,11 +9,8 @@ #include #include #include +#include -#define QCOM_RNG_REG_SIZE 0x1000 - -#define QCOM_RNG_DATA_OUT 0x0 -#define QCOM_RNG_STATUS 0x4 #define QCOM_RNG_STATUS_DATA_AVAIL_BMSK 0x1 #define QCOM_RNG_TIMEOUT_US 1000000 @@ -31,25 +28,28 @@ TEE_Result hw_get_random_bytes(void *buf, size_t len) uint32_t val = 0; uint64_t to = 0; - if (!rng.va) + if (!rng.va) { + EMSG("QCOM RNG: not initialized"); return TEE_ERROR_NOT_SUPPORTED; + } - if (!out || !len) + if (!out || !len) { + EMSG("QCOM RNG: invalid parameters"); return TEE_ERROR_BAD_PARAMETERS; + } to = timeout_init_us(QCOM_RNG_TIMEOUT_US); while (len) { if (!(io_read32(rng.va + QCOM_RNG_STATUS) & QCOM_RNG_STATUS_DATA_AVAIL_BMSK)) { - if (timeout_elapsed(to)) + if (timeout_elapsed(to)) { + EMSG("QCOM RNG: timeout waiting for data"); return TEE_ERROR_BUSY; + } continue; } - while ((val = io_read32(rng.va + QCOM_RNG_DATA_OUT)) == 0) { - if (timeout_elapsed(to)) - return TEE_ERROR_BUSY; - } + val = io_read32(rng.va + QCOM_RNG_DATA_OUT); for (size_t i = 0; i < sizeof(val) && len; i++) { *out++ = (uint8_t)(val >> (i * 8)); @@ -64,8 +64,10 @@ static TEE_Result qcom_csrng_init(void) { rng.va = (vaddr_t)core_mmu_add_mapping(MEM_AREA_IO_SEC, rng.pa, QCOM_RNG_REG_SIZE); - if (!rng.va) + if (!rng.va) { + EMSG("QCOM RNG: failed to map PA=0x%08"PRIxPA, rng.pa); return TEE_ERROR_GENERIC; + } return TEE_SUCCESS; } From de75dd9699506d98cb4c90494cdd3d408ae69152 Mon Sep 17 00:00:00 2001 From: mrehman Date: Tue, 8 Sep 2026 16:28:09 +0530 Subject: [PATCH 2/4] plat-qcom: wildcat: nord: enable PRNG support Enable CSRNG support for the Nord platform. Add the required platform configuration to expose the CSRNG driver to OP-TEE. Validation: - Build verified on Nord - CSRNG functionality validated on Nord Signed-off-by: mrehman --- core/arch/arm/plat-qcom/wildcat/nord/target.mk | 4 ++++ core/arch/arm/plat-qcom/wildcat/nord/target_config.h | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/core/arch/arm/plat-qcom/wildcat/nord/target.mk b/core/arch/arm/plat-qcom/wildcat/nord/target.mk index c774f510f..500d207db 100644 --- a/core/arch/arm/plat-qcom/wildcat/nord/target.mk +++ b/core/arch/arm/plat-qcom/wildcat/nord/target.mk @@ -11,3 +11,7 @@ $(call force,CFG_TEE_CORE_NB_CORE,18) CFG_TZDRAM_START ?= 0xBC280000 CFG_TEE_RAM_VA_SIZE ?= 0x00200000 CFG_TA_RAM_VA_SIZE ?= 0x07B80000 + +# Enable the Qualcomm CSRNG hardware RNG driver. +# Register offsets and base address are defined in target_config.h. +$(call force,CFG_QCOM_CSRNG,y) diff --git a/core/arch/arm/plat-qcom/wildcat/nord/target_config.h b/core/arch/arm/plat-qcom/wildcat/nord/target_config.h index 3d7065ff7..58fdba42e 100644 --- a/core/arch/arm/plat-qcom/wildcat/nord/target_config.h +++ b/core/arch/arm/plat-qcom/wildcat/nord/target_config.h @@ -18,4 +18,9 @@ #define DRAM2_BASE ULL(0x8800000000) #define DRAM2_SIZE ULL(0x3800000000) +#define QCOM_RNG_REG_BASE UL(0x010C0000) +#define QCOM_RNG_REG_SIZE UL(0x2000) +#define QCOM_RNG_DATA_OUT 0x1000 +#define QCOM_RNG_STATUS 0x1004 + #endif /* TARGET_CONFIG_H */ From c327295eb3271cd994676cda57c4b19839464816 Mon Sep 17 00:00:00 2001 From: mrehman Date: Tue, 8 Sep 2026 16:28:36 +0530 Subject: [PATCH 3/4] plat-qcom: bruin: shikra: enable PRNG support Enable CSRNG support for the Shikra platform. Add the required platform configuration to expose the CSRNG driver to OP-TEE. Validation: - Build verified on Shikra - CSRNG functionality validated on Shikra Signed-off-by: mrehman --- core/arch/arm/plat-qcom/bruin/shikra/target.mk | 5 ++++- core/arch/arm/plat-qcom/bruin/shikra/target_config.h | 5 +++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/core/arch/arm/plat-qcom/bruin/shikra/target.mk b/core/arch/arm/plat-qcom/bruin/shikra/target.mk index 14ae1120a..359291ca6 100644 --- a/core/arch/arm/plat-qcom/bruin/shikra/target.mk +++ b/core/arch/arm/plat-qcom/bruin/shikra/target.mk @@ -1 +1,4 @@ -# Placeholder for target specific configs. +# Enable the Qualcomm CSRNG hardware RNG driver. +# Shikra uses the legacy PRNG block via HWKM MMIO. +# Register offsets and base address are defined in target_config.h. +$(call force,CFG_QCOM_CSRNG,y) diff --git a/core/arch/arm/plat-qcom/bruin/shikra/target_config.h b/core/arch/arm/plat-qcom/bruin/shikra/target_config.h index e2a4aeb39..7cabfdd72 100644 --- a/core/arch/arm/plat-qcom/bruin/shikra/target_config.h +++ b/core/arch/arm/plat-qcom/bruin/shikra/target_config.h @@ -14,4 +14,9 @@ #define IMEM_BASE UL(0x0c100000) #define IMEM_SIZE UL(0x00020000) +#define QCOM_RNG_REG_BASE UL(0x04450000) +#define QCOM_RNG_REG_SIZE UL(0x00020000) +#define QCOM_RNG_DATA_OUT 0x1000 +#define QCOM_RNG_STATUS 0x1004 + #endif /* TARGET_CONFIG_H */ From b21496d9eb1487d6eeb17173f8db7600b34d9b67 Mon Sep 17 00:00:00 2001 From: mrehman Date: Tue, 8 Sep 2026 16:29:09 +0530 Subject: [PATCH 4/4] plat-qcom: hoya: update PRNG base address configuration Move the PRNG base address definition from the common Hoya configuration into the platform-specific target configurations. This avoids macro redefinition warnings and allows platform-specific PRNG base addresses to be maintained independently for Kodiak and Lemans. Validation: - Build verified on Kodiak - Build verified on Lemans Signed-off-by: mrehman --- core/arch/arm/plat-qcom/hoya/arch_config.h | 1 - core/arch/arm/plat-qcom/hoya/kodiak/target_config.h | 4 ++++ core/arch/arm/plat-qcom/hoya/lemans/target_config.h | 5 +++++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/core/arch/arm/plat-qcom/hoya/arch_config.h b/core/arch/arm/plat-qcom/hoya/arch_config.h index 11fc5ab44..b603fbf8e 100644 --- a/core/arch/arm/plat-qcom/hoya/arch_config.h +++ b/core/arch/arm/plat-qcom/hoya/arch_config.h @@ -11,7 +11,6 @@ #define GICR_BASE UL(0x17a60000) #define RAMBLUR_PIMEM_REG_BASE UL(0x610000) -#define QCOM_RNG_REG_BASE UL(0x010D1000) #define AOP_MSG_RAM_BASE UL(0x0C300000) #define AOP_MSG_RAM_SIZE UL(0x00100000) diff --git a/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h b/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h index 77354f49e..a43e9432d 100644 --- a/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h +++ b/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h @@ -39,4 +39,8 @@ #define IRIS_BASE UL(0x0aa00000) #define IRIS_SIZE ULL(0x00200000) +#define QCOM_RNG_REG_BASE UL(0x010D0000) +#define QCOM_RNG_REG_SIZE UL(0x00020000) +#define QCOM_RNG_DATA_OUT 0x1000 +#define QCOM_RNG_STATUS 0x1004 #endif /* TARGET_CONFIG_H */ diff --git a/core/arch/arm/plat-qcom/hoya/lemans/target_config.h b/core/arch/arm/plat-qcom/hoya/lemans/target_config.h index 757c67c61..552d35595 100644 --- a/core/arch/arm/plat-qcom/hoya/lemans/target_config.h +++ b/core/arch/arm/plat-qcom/hoya/lemans/target_config.h @@ -94,4 +94,9 @@ #define TITAN_SS_BASE UL(0x0ac00000) #define TITAN_SS_SIZE UL(0x00200000) + +#define QCOM_RNG_REG_BASE UL(0x010D0000) +#define QCOM_RNG_REG_SIZE UL(0x00020000) +#define QCOM_RNG_DATA_OUT 0x1000 +#define QCOM_RNG_STATUS 0x1004 #endif /* TARGET_CONFIG_H */