From e24f45f2180a252ded110decd63ef32f667a00ac Mon Sep 17 00:00:00 2001 From: Flavien Solt Date: Sat, 22 Aug 2026 13:41:35 +0800 Subject: [PATCH] [ara_dispatcher] Fix vector CSR register sources --- CHANGELOG.md | 1 + hardware/src/ara_dispatcher.sv | 16 ++++++++-------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 556d421ea..998f8ca67 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ### Fixed + - Read vector CSR values from the register LSBs - Fix dump vtrace script for vsetvli instructions without x0 (ideal dispatcher) - Fix Pathfinder and FFT performance - Stall Ara and wait for ara_idle upon CSR write/read diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv index e5f9e06d5..5a8aa27b7 100644 --- a/hardware/src/ara_dispatcher.sv +++ b/hardware/src/ara_dispatcher.sv @@ -3394,16 +3394,16 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( acc_resp_o.result = csr_vstart_q; end riscv::CSR_VXRM: begin - csr_vxrm_d = vxrm_t'(acc_req_i.rs1[16:15]); + csr_vxrm_d = vxrm_t'(acc_req_i.rs1[1:0]); acc_resp_o.result = vlen_t'(csr_vxrm_q); end riscv::CSR_VXSAT: begin - csr_vxsat_d = vxsat_e'(acc_req_i.rs1[15]); + csr_vxsat_d = vxsat_e'(acc_req_i.rs1[0]); acc_resp_o.result = vlen_t'(csr_vxsat_q); end riscv::CSR_VCSR: begin - csr_vxrm_d = vxrm_t'( acc_req_i.rs1[17:16] ); - csr_vxsat_d = vxsat_e'( acc_req_i.rs1[15] ); + csr_vxrm_d = vxrm_t'( acc_req_i.rs1[2:1] ); + csr_vxsat_d = vxsat_e'( acc_req_i.rs1[0] ); acc_resp_o.result = vlen_t'( { csr_vxrm_q, csr_vxsat_q } ); end default: illegal_insn = 1'b1; @@ -3432,16 +3432,16 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( else illegal_insn = 1'b1; end riscv::CSR_VXRM: begin - csr_vxrm_d = csr_vxrm_q | vxrm_t'(acc_req_i.rs1[16:15]); + csr_vxrm_d = csr_vxrm_q | vxrm_t'(acc_req_i.rs1[1:0]); acc_resp_o.result = vlen_t'(csr_vxrm_q); end riscv::CSR_VXSAT: begin - csr_vxsat_d = csr_vxsat_q | vxsat_e'(acc_req_i.rs1[15]); + csr_vxsat_d = csr_vxsat_q | vxsat_e'(acc_req_i.rs1[0]); acc_resp_o.result = vlen_t'(csr_vxsat_q); end riscv::CSR_VCSR: begin - csr_vxrm_d = csr_vxrm_q | vxrm_t'(acc_req_i.rs1[17:16]); - csr_vxsat_d = csr_vxsat_q | vxsat_e'(acc_req_i.rs1[15]); + csr_vxrm_d = csr_vxrm_q | vxrm_t'(acc_req_i.rs1[2:1]); + csr_vxsat_d = csr_vxsat_q | vxsat_e'(acc_req_i.rs1[0]); acc_resp_o.result = vlen_t'( { csr_vxrm_q, csr_vxsat_q } ); end default: illegal_insn = 1'b1;