Indexed Load/Store: Hang and Valid-High-Forever when SEW ≠ EEW (vloxei, vsoxei, vluxei, vsuxei)

[BilalAli10x]

Overview

During architectural verification of RVV memory operations on ARA RTL
(VLEN=256, NrLanes=2), the following instruction categories were verified:

• Unit-stride load/store (vle8/16/32/64, vse8/16/32/64) — All Pass ✅
• Constant-stride load/store (vlse8/16/32/64, vsse8/16/32/64) — All Pass ✅
• Whole-register load/store (vl1r–vl8r, vs1r–vs8r) — All Pass ✅
• Fault-only-first (vle8ff/16ff/32ff/64ff) — All Pass ✅
• Mask load/store (vlm.v, vsm.v) — All Pass ✅

Assembly tests and test plan for all above instructions will be submitted
in the pull request.

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Indexed Load/Store: Two Failure Modes Observed

During verification of indexed instructions (vloxei, vsoxei, vluxei, vsuxei),
two failure modes were observed when Data SEW ≠ Index EEW. Both are reported
as failures in the test plan and will be submitted as failing cases in the PR.

The results matrix below shows all configurations tested at VLMAX:

All tests in the above matrix are run at VLMAX (VL = maximum elements).

Legend:

• P = Pass
• H = Hang — simulation stuck, requires Ctrl+C
• VH = addrgen_operand_valid Signal High — Never Goes Low
• NV = Not Valid — Invalid combination per RVV 1.0 specification

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Key Observations from the Matrix

• When SEW = EEW — all test cases pass
• When SEW < EEW — simulation hangs and must be stopped with Ctrl+C
• When SEW > EEW — addrgen_operand_valid signal remains high even after the
  test case completes. When the next test case starts, instead of fetching
  new operand values, it reuses the stale values because addrgen_operand_valid is
  already high — causing that test case to fail

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Failure Type A — Hang (SEW < EEW)

Example: vloxei16.v — SEW=e8, LMUL=mf2, VL=VLMAX=16

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Failure Type B — Valid Signal High Never Goes Low (SEW > EEW)

Example: vloxei16.v — SEW=e32, LMUL=m1, VL=VLMAX=8

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VL Values Where Neither Hang Nor Valid-High Occurs

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vloxei8.v, vluxei8.v

LMUL	SEW	VLMAX	VL where issue does not occur
m1	e32	8	4
m1	e64	4	2
m2	e16	32	16 ⚠
m2	e32	16	4
m2	e64	8	2
m4	e16	64	8
m4	e32	32	4
m4	e64	16	2
m8	e16	128	8
m8	e32	64	4
m8	e64	32	4 ⚠

⚠ m2/e16: VL=16 observed, expected VL=8 based on pattern
⚠ m8/e64: VL=4 observed, expected VL=2 based on pattern

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vsoxei8.v, vsuxei8.v

LMUL	SEW	VLMAX	VL where issue does not occur
m1	e16	16	8
m1	e64	4	2
m2	e16	32	8
m2	e32	16	8 ⚠
m2	e64	8	2
m4	e16	64	8
m4	e32	32	8 ⚠
m4	e64	16	2
m8	e16	128	8
m8	e32	64	8 ⚠
m8	e64	32	2

⚠ m2/e32: VL=8 observed, expected VL=4 based on pattern
⚠ m4/e32: VL=8 observed, expected VL=4 based on pattern
⚠ m8/e32: VL=8 observed, expected VL=4 based on pattern

Compared to vloxei8.v / vluxei8.v:

• m1/e16 (VL=8) — additional case, not present in load variant
• m1/e32 — passes completely in store variant, no issue observed

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vloxei16.v, vluxei16.v

LMUL	SEW	VLMAX	VL where issue does not occur
mf2	e8	16	8
m1	e8	32	8
m1	e32	8	4
m1	e64	4	2 ⚠
m2	e8	64	8
m2	e32	16	4
m2	e64	8	2
m4	e8	128	8
m4	e32	32	8 ⚠
m4	e64	16	2
m8	e32	64	4
m8	e64	32	2

⚠ m1/e64: VL=2 passes without mask but fails with mask
⚠ m4/e32: VL=8 observed, expected VL=4 based on pattern

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vsoxei16.v, vsuxei16.v

LMUL	SEW	VLMAX	VL where issue does not occur
mf2	e8	16	8
m1	e8	32	8
m1	e64	4	2
m2	e8	64	8
m2	e32	16	8 ⚠
m2	e64	8	2
m4	e8	128	8
m4	e32	32	8 ⚠
m4	e64	16	2
m8	e32	64	8 ⚠
m8	e64	32	2

⚠ m2/e32: VL=8 observed, expected VL=4 based on pattern
⚠ m4/e32: VL=8 observed, expected VL=4 based on pattern
⚠ m8/e32: VL=8 observed, expected VL=4 based on pattern

Compared to vloxei16.v / vluxei16.v:

• m1/e32 — passes completely in store variant, no issue observed

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vloxei32.v, vluxei32.v, vsoxei32.v, vsuxei32.v

LMUL	SEW	VLMAX	VL where issue does not occur
mf4	e8	8	4
mf2	e8	16	4
mf2	e16	8	4
m1	e8	32	4
m1	e16	16	4
m1	e64	4	2
m2	e8	64	4
m2	e16	32	4
m2	e64	8	2
m4	e16	64	4
m4	e64	16	2
m8	e64	32	2

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vloxei64.v, vluxei64.v, vsoxei64.v, vsuxei64.v

LMUL	SEW	VLMAX	VL where issue does not occur
mf8	e8	4	2
mf4	e8	8	2
mf4	e16	4	2
mf2	e8	16	2
mf2	e16	8	2
mf2	e32	4	2
m1	e8	32	2
m1	e16	16	2
m1	e32	8	2
m2	e16	32	2
m2	e32	16	2
m4	e32	32	2