There have been several cases of conflicts between code executing on the ARM and SHARC cores when trying to access peripherals. Code targeting the ARM and SHARC cores is often implemented by different people and sometimes different companies. To prevent these conflicts from occurring, access to hardware should be defined using the System Protection Unit (SPU) and System Memory Protection Unit (SMPU).
There have been several cases of conflicts between code executing on the ARM and SHARC cores when trying to access peripherals. Code targeting the ARM and SHARC cores is often implemented by different people and sometimes different companies. To prevent these conflicts from occurring, access to hardware should be defined using the System Protection Unit (SPU) and System Memory Protection Unit (SMPU).