Add Eyeriss v2 CNN accelerator

[mguthaus]

Design: Eyeriss v2 CNN Accelerator

Repository: https://github.com/BoooC/CNN-Accelerator-Based-on-Eyeriss-v2
License: MIT
Language: Verilog (84%), SystemVerilog (12%)
Stars: 139

Description

A flexible and energy-efficient accelerator for sparse CNNs based on the Eyeriss v2 architecture. Features a hierarchical mesh NoC, PE clusters with row-stationary dataflow, CSC encoder for sparsity exploitation, and configurable cluster groups.

Why it's a good benchmark candidate

• New architecture: Hierarchical mesh NoC + systolic PE clusters — a design style not covered by the existing suite. Complements gemmini (systolic array) and cnn (NNGen) with a fundamentally different dataflow-oriented accelerator architecture.
• Industry-relevant: Eyeriss v2 is a seminal ML accelerator architecture from MIT; this is a faithful third-party RTL implementation.
• Large design: Multi-level hierarchy (PE → PE Cluster → Cluster Group → TOP) with routers, GLB clusters, activation units, pooling, quantization, and I/O processing — significantly more complex than existing accelerator benchmarks.
• ASIC-aware: Authors mention OpenROAD + NanGate 45nm synthesis in their README (though their ASIC config is not open-sourced — we would create our own).

Estimated complexity

• Gate count: Large (hierarchical mesh NoC + multiple PE clusters + GLB + control logic)
• Memories: Yes — GLB (global buffer) and PE-level scratchpads will need FakeRAM
• IO count: Medium-high (data buses, control, UART debug interface)

Verification

Testbenches in FPGA_design/test/tb/ with test data generation scripts in FPGA_design/test/gen_test_data/. Verified on PYNQ-Z2 FPGA running LeNet-5 inference with a Python GUI for handwritten digit recognition.

Conversion notes

Primarily Verilog with some SystemVerilog — may need sv2v or yosys-slang for the SV portions. FPGA-specific constructs (UART, display) would be excluded; core accelerator datapath is target-independent.

Target platforms

• asap7
• nangate45
• sky130hd