Fix FIFO queue size#90
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Pull request overview
This PR adjusts the STM32L4 SPI bus reconfiguration path to correctly set the RX FIFO threshold (FRXTH) based on the configured word size, addressing corrupted reads when using >8-bit (e.g., 16-bit) SPI devices.
Changes:
- Set
FRXTHto half-full for >8-bit words and quarter-full for ≤8-bit words when (re)configuring a device. - Add an in-code explanation of why
FRXTHmust track word width to prevent RXNE timing issues.
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Fix 16 bit SPI devices