P6 follow-up: Create VectorVsRasterParityTests.swift and flip vector fast-path build-time default

[dsmithnh3]

After P6-5 shipped (commit 4a2284f9), VectorExtractionFeatureFlags.enableVectorFastPath is build-time false with a UserDefaults runtime override (P&ID Settings → Enable vector fast path (experimental)). The build-time default cannot flip to true until a parity test corpus exists.

Acceptance criteria

1. Create Tests/CircuitProTests/VectorVsRasterParityTests.swift.
2. Fixture corpus under Tests/Fixtures/VectorParity/:
   • autocad-export.pdf (vector-dominant)
   • microstation-export.pdf (vector-dominant)
   • visio-export.pdf (vector-dominant)
   • One scanned/raster-dominant PDF as a negative control.
3. For each vector fixture, run both pipelines and assert:
   • Polyline count parity within ±10%.
   • Total polyline length parity within ±5%.
   • Text detection count parity within ±5%.
4. For the raster fixture, assert classifier verdict is .rasterDominant and the fast path falls back correctly.
5. Once green on CI, flip VectorExtractionFeatureFlags.enableVectorFastPath = true in a separate PR and update docs/architecture/ai-pipeline.md to mark the vector path [Implemented] (no longer [Experimental]).

References

• Feature flag: CircuitPro/Features/AI/VectorExtraction/VectorExtractionFeatureFlags.swift
• Settings UI: CircuitPro/Features/Settings/PIDSettingsView.swift:48,196
• Implementation: CircuitPro/Core/Managers/AIAnalysisManager.swift (post-P6-9 reorder)
• Lint-debt tracking note: docs/lint-debt-tracking.md "P6 wiring follow-ups"